Amplifiers – With semiconductor amplifying device – Including differential amplifier
Reexamination Certificate
2005-10-18
2005-10-18
Choe, Henry (Department: 2817)
Amplifiers
With semiconductor amplifying device
Including differential amplifier
C330S261000
Reexamination Certificate
active
06956434
ABSTRACT:
A biasing scheme for a MOSFET that mitigates the MOSFET body effect. The biasing scheme can be realized replicating the voltage at the source terminal of a MOSFET and applying this replicated voltage to the body terminal. In this manner, the effect of the body transconductance, at high frequencies, becomes a function of the ratio of the well-to-substrate capacitance of the MOSFET to the sum of the well-to-substrate capacitance and the source-to-body capacitance of the transistor. At high frequencies, the biasing scheme mitigates the reduction in gain of a source follower caused by the body effect of a driven MOSFET within the source follower, improves the stability of a feedback network established by a gain boosting amplifier and the driven MOSFET by contributing a negative half plane zero to the transfer function of the feedback network, and reduces the power consumed by the gain boosting amplifier.
REFERENCES:
patent: 3609414 (1971-09-01), Pleshko et al.
patent: 4550284 (1985-10-01), Sooch
patent: 4837460 (1989-06-01), Uchida
patent: 5157279 (1992-10-01), Lee
patent: 5323121 (1994-06-01), Butler
patent: 5689144 (1997-11-01), Williams
patent: 5703522 (1997-12-01), Arimoto et al.
patent: 5880620 (1999-03-01), Gitlin et al.
patent: 5905402 (1999-05-01), Kim et al.
patent: 5936456 (1999-08-01), Naka
patent: 6023195 (2000-02-01), Nakano et al.
patent: 6037808 (2000-03-01), Houston et al.
patent: 6064262 (2000-05-01), Wang
patent: 6225846 (2001-05-01), Wada et al.
patent: 6229187 (2001-05-01), Ju
patent: 6271713 (2001-08-01), Krishnamurthy
patent: 6377120 (2002-04-01), Hsieh
patent: 6469568 (2002-10-01), Toyoyama et al.
patent: 6496066 (2002-12-01), Colonna et al.
patent: 6724258 (2004-04-01), Fayed
Bernstein, K. et al., “High-Speed Design Styles Leverage IBM Technology Prowess,”MicroNews,vol. 4, No. 3, 1998.Printed from http://www.chips.ibm.com/micronews/vol4_no3/highspeed.html.
Bult, K. and Geelen, G.J.G.M., “A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain,”IEEE Journal of Solid-State Circuits,IEEE, vol. 25, No. 6, Dec. 1990, pp. 1379-1384.
Geerts, Y. et al., “A 3.3-V, 15-bit, Delta-Sigma ADC with a Signal Bandwidth of 1.1 MHz for ADSL Applications,”IEEE Journal of Solid States Circus,IEEE, vol. 34, No. 7, Jul. 1999, pp. 927-936.
Marques, A.M. et al., “A 15-b Resolution 2-MHz Nyquist Rate ΔΣ ADC in a 1-μm CMOS Technology,”IEEE Journal of Solid-State Circuits,IEEE, vol. 33, No. 7, Jul. 1998, pp. 1065-1075.
Gray, P.R. et al.,Analysis and Design of Analog Integrated Circuits: Fourth Edition,John Wiley & Sons, 2001, pp. ix-xviii, 49-59, 131-145 and 253-336.
Copy of European Search Report for Appln. No. EP 02 25 0156, issued Jun. 4, 2003, 3 pages.
Choe Henry
Sterne Kessler Goldstein & Fox P.L.L.C.
LandOfFree
MOSFET well biasing scheme that mitigates body effect does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MOSFET well biasing scheme that mitigates body effect, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOSFET well biasing scheme that mitigates body effect will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3460155