MOSFET well biasing scheme that migrates body effect

Details MOSFET well biasing scheme that migrates body effect MOSFET well biasing scheme that migrates body effect

2001-08-30

2004-01-20

Callahan, Timothy P. (Department: 2816)

Amplifiers

With semiconductor amplifying device

Including field effect transistor

C330S296000, C327S534000

Reexamination Certificate

active

06680650

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a biasing scheme that mitigates the MOSFET body effect and reduces the effect of the well-to-substrate capacitance on the MOSFET. More specifically, the present invention, at high frequencies, mitigates the reduction in gain of a source follower caused by the body effect of a driven MOSFET within the source follower, improves the stability of a feedback network established by a gain boosting amplifier and the driven MOSFET, and reduces the power consumed by the gain boosting amplifier.
2. Background Art
Operational amplifiers used in precision switched capacitor circuits are faced with very stringent requirements for their settling behavior and their dc performance. These requirements are particularly important when they are used in high speed, high resolution analog-to-digital converters such as those described in A. M. Marques et al., “A 15b resolution Delta Sigma ADC in a lum CMOS technology”,
IEEE Journal of Solid State Circuits
, pp. 1065-75, July 1998; and Yves Geerts et al., “A 3.3V, 15-bit, Delta-Sigma ADC with a Signal Bandwidth of 1.1 MHz for ADSL applications”,
IEEE Journal of Solid State Circuits
, pp. 927-36, July 1999. Often for such applications, the operational amplifiers use a gain boosted folded cascode topology because it can support high gain at wide bandwidths.
FIG. 1
is a schematic diagram of an exemplary conventional gain boosted folded cascode operational amplifier
100
. The principles underlying the discussion in relation to
FIG. 1
are not intended to be limited to the particular topology of operational amplifier
100
.
In
FIG. 1
, operational amplifier
100
comprises a first active load leg
102
and a second active load leg
104
connected in parallel between a supply voltage “V
DD
”
106
and an analog ground “V
AG
”
108
. (The skilled artisan would appreciate that, alternatively, a second supply voltage “V
SS
” could be used in place of V
AG
108
.) First active load leg
102
comprises a cascoded series of PMOSFETs “M1”
110
and “M3”
112
; and a cascoded series of NMOSFETs “M5”
114
and “M7”
116
. Second active load leg
104
comprises a cascoded series of PMOSFETs “M2”
118
and “M4”
120
; and a cascoded series of NMOSFETs “M6”
122
and “M8”
124
.
The gate terminals of M1
110
and M2
118
are together connected to a first bias voltage “V
BP
”
126
to hold the MOSFETs in saturation. The source terminal of M3
112
is connected to the inverting terminal of a gain boosting amplifier “A1”
128
, while the output of A1
128
is connected to the gate terminal of M3
112
such that a feedback network “FN
1
”
130
is established. The source terminal of M4
120
is connected to the inverting terminal of a gain boosting amplifier “A2”
132
, while the output of A2
132
is connected to the gate terminal of M4
120
such that a feedback network “FN
2
”
134
is established. The noninverting terminals of A1
128
and A2
132
are together connected to a second bias voltage “V
PREF
”
136
to hold the corresponding MOSFETs (i.e., M3
112
and M4
120
) in saturation.
The source terminal of M5
114
is connected to the inverting terminal of a gain boosting amplifier “A3”
138
, while the output of A3
138
is connected to the gate terminal of M5
114
such that a feedback network “FN
3
”
140
is established. The source terminal of M6
122
is connected to the inverting terminal of a gain boosting amplifier “A4”
142
, while the output of A4
142
is connected to the gate terminal of M4
122
such that a feedback network “FN
4
”
144
is established. The noninverting terminals of A3
138
and A4
142
are together connected to a third bias voltage “V
NREF
”
146
to hold the corresponding MOSFETs (i.e., M5
114
and M6
122
) in saturation. The gate terminals of M7
116
and M8
124
are together connected to a fourth bias voltage “V
BN
”
148
to hold the MOSFETs in saturation.
Each feedback network (e.g., FN
1
130
, FN
2
134
, FN
3
140
, or FN
4
144
), acts to hold the voltage at the source terminal of its driven MOSFET (e.g., M3
112
, M4
120
, M5
114
, or M6
122
) equal to the bias voltage (e.g., V
PREF
136
or V
NREF
146
) applied to the noninverting terminal of the corresponding gain boosting amplifier (e.g., A1
128
, A2
132
, A3
138
, or A4
142
). For example, A1
128
detects any difference in voltage between the source terminal of M3
112
and V
PREF
136
, and drives the voltage at the gate terminal of M3
112
to eliminate the difference.
Operational amplifier
100
further comprises a differential amplifier
150
. Differential amplifier
150
comprises a current source “I
TAIL
”
152
, a first amplifying PMOSFET “M9”
154
, and a second amplifying PMOSFET “M10 ”
156
. The source terminals of M9
154
and M10
156
are connected together in parallel. I
TAIL
152
is connected between V
DD
106
and the source terminals of M9
154
and M10
156
. The drain terminal of M9
154
is connected to the drain terminal of M7
116
. The drain terminal of M10
156
is connected to the drain terminal of M8
124
. M9
154
and M10
156
comprise a differential pair and act to control the distribution of current flowing from I
TAIL
152
between V
DD
106
and V
AG
108
. The sum of the current flowing through both M9
154
and M10
156
equals I
TAIL
152
.
Operational amplifier
100
receives a differential input signal and produces a differential output signal. The differential input signal comprises a positive input signal “V
in
+
”
158
and a negative input signal “V
in
−
”
160
. V
in
+
158
is received at the gate terminal of M9
154
. V
in
−
160
is received at the gate terminal of M10
156
. The differential output signal comprises a positive output signal “V
out
+
”
162
and a negative output signal “V
out
−
”
164
. V
out
+
162
is presented at the drain terminal of M5
114
. V
out
−
164
is presented at the drain terminal of M6
122
.
So, for example, as V
in
+
158
rises with respect to V
in
−
160
, the portion of the total current of I
TAIL
152
that flows through M9
154
(i.e., a PMOSFET) and M7
116
becomes smaller, while the portion that flows through M10
156
and M8
124
becomes larger. With the gate-to-source voltages of M7
116
and M8
124
(i.e., NMOSFETs) held equal to V
BN
148
, the decreased amount of current flowing through M7
116
causes its drain-to-source voltage to decrease, while the increased amount of current flowing through M8
124
causes its drain-to-source voltage to increase. Because the source terminal of M7
116
is connected to V
AG
108
, the decrease in its drain-to-source voltage is realized as a lower voltage at its drain terminal. Likewise, because the source terminal of M8
124
is connected to V
AG
108
, the increase in its drain-to-source voltage is realized as a higher voltage at its drain terminal. So, in first active load leg
102
, there is a larger drop in voltage potential between V
DD
106
and the drain terminal of M7
116
, while in second active load leg
104
, there is a smaller drop in voltage potential between V
DD
106
and the drain terminal of M8
124
. Initially, this causes less current to flow through first active load leg
102
and more current to flow through second active load leg
104
. However, the MOSFETs in these legs strive to maintain the current flowing through them at a constant level.
As the drain terminal of M7
116
is connected to the source terminal of M5
114
, the voltage at the source terminal of M5
114
also falls so that the gate-to-source voltage of M5
114
increases. Because the current flowing through M5
114
strives to remain constant, the increase in the gate-to-source voltage of M5
114
(i.e., a NMOSFET) causes a decrease in its drain-to-source voltage of a larger magnitude than the increase in the gate-to-source voltage. Via FN
3
140
, this effect is enhanced by A3
138
, which receives the lower voltage at the source terminal of M5
114
, inverts it, amplifies it, and applies i

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