MOSFET-type device with higher driver current and lower...

Reexamination Certificate

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C257S328000

Reexamination Certificate

active

06213869

ABSTRACT:

TECHNICAL FIELD
This invention relates to transistor devices fabricated as part of integrated circuits, and more particularly, to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) type device with an especially designed capacitor coupled between the gate and the body of a MOSFET such that the MOSFET has a threshold voltage of lower magnitude when the MOSFET is turned on for higher drive current and such that the MOSFET has a threshold voltage of higher magnitude when the MOSFET is turned off for lower steady state power dissipation.
BACKGROUND OF THE INVENTION
MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are a common component in integrated circuits fabricated on a semiconductor wafer. The current characteristic of a MOSFET when the MOSFET is turned on is as follows:
I
D
=k
(
V
GS
-V
t
)
2
with I
D
being the drain current of the MOSFET, k being a constant that depends on the size and fabrication parameters of the MOSFET, V
GS
being the gate to source voltage of the MOSFET, and V
t
being the threshold voltage of the MOSFET, as known to one of ordinary skill in the art of electronics.
For better circuit performance, higher speed and thus higher drain current is desired when the MOSFET is turned on. Thus, when the MOSFET is turned on, a threshold voltage V
t
with lower magnitude is desired. On the other hand, for lower steady state power dissipation when the MOSFET is turned off, a threshold voltage with higher magnitude is desired.
Higher device speed and lower power dissipation require opposite constraints on the threshold voltage of a MOSFET. In prior art MOSFETs, the threshold voltage is typically the same for when the MOSFET is turned on and for when the MOSFET is turned off. Therefore, a trade-off between higher device speed and lower steady state power dissipation is considered with the prior art MOSFET device.
However, both higher device speed and lower steady state power dissipation are desired for high performance integrated circuits. Thus, a MOSFET type device is desired that may be designed both for higher device speed when the MOSFET is turned on and for lower steady state power dissipation when the MOSFET is turned off.
SUMMARY OF THE INVENTION
Accordingly, the present invention is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) type device having higher drive current when turned on and having lower steady state power dissipation when turned off. The MOSFET type device is fabricated on a semiconductor substrate. Generally, the MOSFET type device comprises a floating body
1
a
region that is electrically isolated from the semiconductor substrate, a drain region that is formed abutting the floating body region, a source region that is formed abutting the floating body region, and a gate formed on a gate insulator disposed on top of the floating body region between the drain region and the source region. The present invention also includes a coupling capacitor that is operatively coupled between the gate and the floating body region, and the coupling capacitor has a capacitance of C
C
. The floating body region, the drain region, the source region, and the gate form a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The drain region forms a collector of a BJT (Bipolar Junction Transistor), and the floating body region forms a base of the BJT, and the source region forms an emitter of the BJT. The MOSFET is turned on to provide the drive current when a voltage change of V
dd
is applied on the gate with respect to the source of the MOSFET. In accordance with the present invention, the capacitance, C
C
, of the coupling capacitor is designed such that [V
body(I)
+(C
C
*V
dd
)/(C
C
+C
P
)]>V
C
to provide a positive voltage at the floating body region with respect to the source region when the MOSFET is turned on, where V
body(I)
is an initial voltage at the floating body region immediately before the voltage change of V
dd
is applied on the gate with respect to the source of the MOSFET, where C
P
is a capacitance of an effective parasitic capacitor at the floating body region, and where V
C
is a clamping voltage of a diode formed by the base and the emitter of the BJT.
In this manner, the design of the capacitance C
C
of the coupling capacitor, such that [V
body(I)
+(C
C
*V
dd
)/(C
C
+C
P
)]>V
C
, results in the BJT turning on when the MOSFET is turned on. In addition, the positive voltage at the floating body region with respect to the source region, when the MOSFET is turned on, results in a threshold voltage of lower magnitude according to the body effect of the MOSFET.
Furthermore, the capacitance, C
C
, of the coupling capacitor may be designed such that [V
C
−(C
C
*V
dd
)/(C
C
+C
P
)] is a negative value to provide a negative voltage at the floating body region with respect to the source region when the MOSFET is turned off. In this manner, the design of the capacitance C
C
of the coupling capacitor, such that [V
C
−(C
C
*V
dd
)/(C
C
+C
P
)] is a negative value, results in the BJT turning off when the MOSFET is turned off. In addition, the negative voltage at the floating body region with respect to the source region, when the MOSFET is turned off, results in a threshold voltage of higher magnitude according to the body effect of the MOSFET. The present invention further includes a mechanism for ensuring that the voltage at the floating body region with respect to ground is at V
body(I)
before the voltage change of V
dd
is applied on the gate with respect to the source of the MOSFET to turn the MOSFET back on.
Thus, with proper design of the capacitance C
C
of the coupling capacitor, the MOSFET type device of the present invention has higher drive current when the MOSFET is turned on and lower steady state power dissipation when the MOSFET is turned off.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.


REFERENCES:
patent: 4618872 (1986-10-01), Baliga
patent: 5559368 (1996-09-01), Hu et al.
patent: 5717241 (1998-02-01), Malhi et al.
patent: 5966032 (1999-10-01), Elrabaa et al.

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