MOSFET test structure for capacitance-voltage measurements

Details MOSFET test structure for capacitance-voltage measurements MOSFET test structure for capacitance-voltage measurements

2000-06-05

2002-10-29

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

With measuring or testing

C438S014000, C438S018000, C438S197000, C324S762010, C324S500000, C257S288000

Reexamination Certificate

active

06472233

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to apparatus and a method related to a test structure for capacitance-voltage (C−V) measurements for very thin oxides.
2. Description of the Related Art
Oxides as thin as 13-15 angstroms have been used as gate dielectrics to fabricate sub-100-nm polysilicon-gated CMOS devices. See, for example, G. C.-F. Yeap et al., Sub-100-nm nMOSFET's with direct tunneling thermal, nitrous, and nitric oxides,” in Proc. 56
th
Annu. Dev. Res. Conf. (DRC), Charlottesville, Va. 1998, pp. 10-11; G. Timp et al., “Low leakage, ultra-thin gate oxides for extremely high performance sub-100-nm nMOSFET's ,” in IEDM Tech. Dig., 1994, pp. 593-596; D. A. Buchanan and S.-H. Lo, “Reliability and integration of ultra-thin gate dielectrics for advanced CMOS,” in Microelectron. Eng., vol. 36, pp. 13-20, 1997; and J. Hauser and K. Ahmed, “Characterization of ultrathin oxides using electrical C−V and I−V measurements,” in National Institutes of Standards and Technology, Gaithersburg, Md., Mar. 23-27, 1998. Characterization of sub-0.1 &mgr;m CMOS devices requires accurate determination of the device material and physical parameters, such as oxide thickness t
ox
, oxide charges Q
,f
, surface doping in the substrate (N
sub
) and polysilicon-gate doping (N
poly
) densities, and interface state density. Although high frequency (HF) C−V, measured on MOS capacitor structures, can be used for estimating t
ox
, Q
,f
and N
sub
, it is necessary to use MOSFET structures to obtain the low-frequency-like (LF) C−V curve in strong inversion to estimate N
poly
, especially for sub-30 Å oxides. With a MOSFET, the inversion layer charge is maintained by the minority carriers supplied by the source and drain junctions. To avoid distortion of the C−V curve due to channel charging effects, it is necessary to use MOSFET structures with proper channel length L, and measurement frequency f, in order to satisfy the condition: 2&pgr;f×&tgr;
gc
<<1, where, &tgr;
gc
∝(L
2
·t
ox
)
−1
is the channel time constant. See P.-M. D. Chow and K.-L. Wang, “A new AC technique for accurate determination of channel charge and mobility in very thin gate MOSFET's ,” in IEEE Trans. Electron Devices, vol. ED-33, pp. 1299, September 1986; U. Lieneweg, “Frequency response of charge transfer in MOS inversion layers,” in Solid-State Electron., vol. 23, pp. 577-583, 1980. This condition sets an upper limit on L for a given frequency f. In addition, accuracy requirements imposes a lower limit on L, in order to minimize gate overlap capacitance parasitic effects, and a lower limit exists on the measurement frequency for any capacitance meter to accurately separate capacitive and conductive components of the measured impedance, especially for sub-20 Å devices.
Anomalous dependence on C−V characteristics on test structure geometry for sub-15 Å oxides have been reported. See Bayomi et al., “Process, characterization and integrity issues for 15 Å gate oxides,” in Proc. 1998 Hewlett-Packard Silicon Technology Conf., Portland, Oreg., Mar. 31-Apr. 3, 1998, pp. 33-38. It was reported that the capacitance measured on large area capacitor or transistor structures show large attenuation in both strong inversion and accumulation bias regimes. The capacitance attenuation was found to increase with increasing the gate area in both bias regimes. A model with distributed gate sheet resistance and bias-dependent tunneling conductance was proposed and used to explain the observed experimental data. However, although the polysilicon gate sheet-resistance may be important in accumulation, the present inventors have determined that the channel resistance will be dominant in strong inversion, especially for MOSFETs with silicided polysilicon gates. This can be seen from the dependence of the strong inversion capacitance roll-off on the channel length, as will be explained in more detail below.
SUMMARY OF THE INVENTION
The invention provides a method and apparatus for test structures for capacitance-voltage measurements for very thin oxides.
A test structure may include a first MOSFET having a channel length less than a predetermined channel length, and a second MOSFET having a channel length less than the predetermined channel length. The first and second MOSFETS are connected in parallel. Device parameters are capable of being extracted from the MOSFET test structure. Effects due to tunneling currents and channel dimensions are considered in determining a terminal capacitance of the MOSFET test structure.
A MOSFET test structure method includes modeling a first MOSFET having a channel length less than a predetermined channel length; and modeling a second MOSFET having a channel length less than the predetermined channel length. The method also includes connecting the first and second MOSFETS in parallel. At least one device parameter is capable of being extracted utilizing the MOSFET test structure.


REFERENCES:
patent: 3882391 (1975-05-01), Liles et al.
patent: 5600578 (1997-02-01), Fang et al.
patent: 5793675 (1998-08-01), Cappelletti et al.
patent: 5821766 (1998-10-01), Kim et al.
patent: 6049104 (2000-04-01), Hshieh et al.
patent: 6069485 (2000-05-01), Long et al.
patent: 6100751 (2000-08-01), De et al.
patent: 6166558 (2000-12-01), Jiang et al.
patent: 6228663 (2001-05-01), Gardner et al.
Ahmed et al. “Impact of tunnel currents and channel resistance on channel inversion layer and poly-gate depletion of Sub-20A oxide MOSFET's” IEEE Transactions on Electron devices vol. 46. No. 8 Aug. 1999.*
Brews et al. “A Test for lateral nonuniformities in MOS devices using only capacitance Curves” Solid-state Electronics vol. 16 1973 pp. 1267-1277.*
Lee et al. “A new rf capacitance method to extract the effective channel length of mosfets using s-parameters” IEEE 0-7803-6304-Mar. 2000 pp. 56-59.*
Yeap, et al., “Sub-100-nm nMOSFET's with direct tunneling termal, nitrous, and nitric oxides, ” Proc. 56thAnnu. Dev. Res. Conf. (DRC), Charlottesville, VA 1998, pp. 10-11.
Timp et al., “Low leakage, ultra-thin gate oxides for extremely high performance sub-100-nm nMOSFET's,” IEDM Tech. Dig., 1994, pp. 593-596.
Buchanan, et al., “Reliability and integration of ultra-thin gate dielectrics for advanced CMOS,” Microelectron. Eng. vol. 36, 1997, pp. 13-20.
Chow, et al., “A new AC technique for accurate determination of channel charge and mobility in very thin Gate MOSFET's,” IEEE Trans. Electron Devices, vol. ED-33, Sep. 1986, pp. 1299.
Lieneweg, “Frequency response of charge transfer in MOS inversion layers,” Solid-State Electron, vol. 23, 1980, pp. 577-583.
Lee, “A Capacitance-Based Method for Experimental Determination of Mettalurgical Channel Length of Submicron LDD MOSFET's”, IEEE Transactons on Electron Devices, vol. 41, No. 3, Mar. 1994, pp. 403-412.
E. Vogel et al., “Modeled Tunnel Currents for High Dielectric Constant Dielectrics”, IEEE Transactions on Electron Devices, Vo. 45, No. 6, Jun., 1998, pp. 1350-1355.
T. Smedes et al., “Influence of Channel Series Resistances on Dynamic MOSFET Behavior”,:1994, pp. 251-254.
C. Wang, “Identification and Measurement of Scaling-Dependent Parasitic Capacitances of Small-Geometry MOSFET's”, IEEE Transactions on Electron Devices, vol. 43, No. 6, Jun. 1996, pp. 965-972.
A. Ernst et al., “A New Z11 Impedance Technique to Extract Mobility and Sheet Carrier Concentration in HFET's and MESFET's”, IEEE Transactions on Electron Devices, vol. 45, No. 1, Jan. 1998, pp. 9-13.
B. Ricco et al., “Characterization of Polysilicon-Gate Depletion in MOS Structures”, IEEE Electron Device Letters, vol. 17, No. 3, Mar., 1996, pp. 103-105.
W. Lin, “A Simple Method for Extracting Average Doping Concentration in the Polysilicon and Silicon Surface Layer Near the Oxide in Polysilicon-Gate MOS Structures”, IEEE Electron Device Letters, vol. 15, No. 2, Feb. 1994, pp. 51-53.
H. Momose et al., Tunneling Gate Oxide Approach to Ultra-High Current Drive In Smal

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