MOSFET structure having reduced gate capacitance

Details MOSFET structure having reduced gate capacitance MOSFET structure having reduced gate capacitance

1991-04-19

1992-06-09

Hille, Rolf

357 233, 357 238, 357 2314, 357 86, H01L 2910, H01L 2968, H01L 2978

Patent

active

051211769

ABSTRACT:
In one embodiment, a vertical MOSFET is formed having a lower gate portion overlying the channel region of the MOSFET and separated from the channel region by a thin gate oxide layer. An upper gate portion is formed overlying the drain of the MOSFET and separated from the drain by a relatively thick oxide layer. In this particular embodiment, since the dielectric thickness between the upper gate portion and the drain is relatively large, the MOSFET exhibits a lower gate-drain capacitance (C.sub.GD) value, while the threshold voltage of the MOSFET remains relatively unchanged. The upper gate portion may be electrically connected to the lower gate portion or may be electrically isolated from the lower gate portion. A preferred method of forming the resulting MOSFET having this lowered C.sub.GD allows the source and body regions to be precisely aligned with the drain edge of the lower gate portion.

REFERENCES:
patent: 4290077 (1981-09-01), Ronen
patent: 4455565 (1984-06-01), Goodman et al.
patent: 4969020 (1990-11-01), Matsushita et al.

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