Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
1997-11-04
2001-07-31
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C326S081000
Reexamination Certificate
active
06268755
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to improvements in electronic circuitry, and more particularly to circuitry and techniques for voltage level adjusting, controlling, and setting.
2. Relevant Background
In many applications, it is desirable or necessary to adjust or shift a voltage level from one electronic stage to an adjacent stage. For example, it is often desirable to shift TTL voltage levels, typically on the order of 0 to 5 volts, to higher voltage levels, for instance, on the order of 0 to V
SHFT
, where V
SHFT
may be 40 volts, or more. However, in the past, level shifters, and particularly, level shifters that use integrated slope control resistors can be susceptible to latching in one state. This, of course, is undesirable.
More specifically, a level shifter circuit
10
, which can be used to drive a large output MOSFET (not shown), according to one prior art embodiment is shown in FIG.
1
. The circuit
10
includes four MOS transistors
11
-
14
. Transistors
11
and
12
are, in the embodiment shown, p-channel MOS devices connected between a voltage source, V
SHFT
,
16
and output nodes
18
and
20
. Transistors
13
and
14
, on the other hand, are n-channel MOS transistors, which are connected respectively between the output nodes
18
and
20
to a reference potential or ground
22
.
An input signal or voltage level on line
24
is applied to the gate of transistor
14
, and is inverted by an inverter
26
and applied to the gate of the N-channel transistor
13
. The gate of the p-channel transistor
12
is connected to the output node
18
, and the gate of the p-channel transister
11
is connected to the output node
20
.
The switching speed of this level shifter will only be a function of the on-resistance of transistors
12
and
14
and the gate charge characteristic of the output MOSFET. As a result, the switching speed may be extremely fast, which may be undesirable, especially when the output is used to drive loads that are prone to cause electromagnetic interference (EMI) due rapidly changing currents in long wires.
To address this problem, a circuit such as the circuit
30
shown in
FIG. 2
, has been proposed. The level shifting circuit
30
includes four transistors,
32
-
35
connected in series between a voltage, V
SHFT
38
and a reference potential such as ground
40
. The gate of p-channel transistor
32
is connected to the drain of the p-channel transistor
33
and, likewise, the gate of the transistor
33
is connected to the drain of transistor
32
.
The input line
42
is connected to the gate of the n-channel transistor
35
, is inverted by an inverter
44
, and is connected to the gate of the n-channel transistor
34
. In the circuit embodiment
30
of
FIG. 2
, a resistor
46
is provided between the drain of the p-channel transistor
33
and the output node
48
. In addition, a resistor
50
is connected between the output node
48
and an output terminal
52
, which may be connected to drive a large MOSFET transistor (not shown), or other appropriate load.
In the circuit
30
of
FIG. 2
, the switching speed is not instantaneous, but is a function of the values of resistors
46
and
50
, since the on-resistance of the transistors
33
and
35
is negligible compared to-the resistances of resistors
46
and
50
.
Although the circuit
30
of
FIG. 2
addresses the above problems caused the instantaneous switching time, the circuit
30
has two problems. The first problem is that while the rise time of the output of the circuit
30
is a function primarily of the value of resistance
50
, the fall time of the output is a function primarily of the series combination of the resistors
46
and
50
. This makes setting the fall time with precision difficult. The second, and more serious, problem is that the ability of the level shifter circuit
30
to switch states is predicated on the ability of transistor
35
to pull the drain of transistor
33
down to the ground potential. This simultaneously switches transistor
32
on. If the value of resistor
50
becomes too large, the operation of the level shifter circuit
30
may be compromised.
SUMMARY OF THE INVENTION
In light of the above, therefore, it is an object of the invention to provide an improved level shifter circuit.
It is another object of the invention to provide a level shifter circuit of the type described that enables the slope of the output signal to be controlled.
It is yet another object of the invention to provide a level shifter circuit of the type described that allows the rise time of the output signal to be controlled independently of the fall time, and visa versa.
It is yet another object of the invention to provide a level shifter circuit of the type described that enables reliable, consistent switching of the circuit.
These and other objects, features and advantages of the invention will be apparent to those skilled in the art from the following detailed description of the invention, when read in conjunction with the accompanying drawings and appended claims.
According to a broad aspect of the invention, a second stage onto a voltage level shifter circuit. The second stage separates the slope control resistors from the level shifting function, and placing the slope control resistors to allow the rise time to be a function of one of the resistors, and the fall time to be a function of the other resistor.
More particularly, according to a broad aspect of the invention, a voltage level shifting circuits is presented that includes a voltage level shifting circuit to change an input voltage to a shifted voltage level. A second stage is connected between a voltage source at the shifted voltage level and the reference potential, or ground. The second stage includes active devices that are controlled by the voltage level shifting circuit. The second stage also includes slope controlling devices to control a slope of a voltage transition at an output in response to an input voltage change. The active devices of the second stage may be transistors connected between the voltage source and the reference potential. The slope controlling devices may be resistors connected in series between the transistors of the second stage, a circuit output being derived from a connected between the resistors. The transistors of the second stage may be MOS transistors.
The voltage level shifting circuit may be of the type that includes first and second transistors connected between the voltage source and a reference potential, and third and fourth transistors connected between the voltage source and the reference potential. An input voltage is connected a gate of the fourth transistor, and an inverted input voltage is connected to a gate of the second transistor. A gate of the first transistor is connected to a drain of the third transistor, and a gate of the third transistor is connected to a drain of the first transistor. The first, second, third and fourth transistors may be MOS transistors.
According to another broad aspect of the invention, a method is presented for controlling transition slopes of a voltage level shifting circuit. The method includes providing first and second series connected slope controlling devices and providing first and second active devices. The method additionally includes interconnecting said slope controlling devices in series between said first and second active devices and interconnecting said first and second active devices and said series connected first and second active devices between a voltage source at a shifted voltage level and reference potential. The step of providing first and second active devices may be performed by providing first and second transistors, and the step of providing first and second active devices may be performed by providing first and second MOS transistors.
REFERENCES:
patent: 5465069 (1995-11-01), Boiron et al.
patent: 5559464 (1996-09-01), Orii et al.
patent: 5666070 (1997-09-01), Merritt et al.
patent: 5748024 (1998-05-01), Takahashi et al.
patent: 5834948 (1998-11-01), Yoshiza
Devore Joseph A.
Grose William E.
Summerlin R. Travis
Brady W. James
Mosby April M.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tran Toan
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