MOSFET Memory chip with single decoder and bi-level interconnect

Details MOSFET Memory chip with single decoder and bi-level interconnect MOSFET Memory chip with single decoder and bi-level interconnect

1975-12-29

1979-05-29

Hecker, Stuart N.

Static information storage and retrieval

Interconnection arrangements

365205, 365230, 365239, G11C 800, G11C 502

Patent

active

041569385

ABSTRACT:
A dynamic random access read/write memory having 4,096 binary storage cells is disclosed. The system utilizes a single set of six address input buffers and one decoder for both row and column address information. The memory array includes two 32.times.64 arrays of dynamic storage cells separated by a row of 64 sense amplifiers each having split sense buses or digit lines extending to each column of memory bits. The decoders are disposed along one edge of the array which is at right angles to the row of sense amplifiers. The column enable lines from the decoders extend through the memory array between parallel row enable lines and then turn and proceed as a different level of interconnect between parallel digit lines to select the addressed sense amplifiers. Each column enable line enables two sense amplifiers which simultaneously read data from two cells of the addressed row. The least significant bit of the six column address inputs is used to make the final one out of two selection of the sense amplifier and thus the cell from which data is to be read or in which data is to be written. The decoder includes circuit means for storing the decode signal identifying a selected row while subsequent column address signals are input to the chip and decoded by the same decoder. Row address data is first input through the six address pins to the chip; the six inputs are sampled and latched in six address buffers; and the six address inputs are then decoded so that a single row enable line is selected and held active dynamically. Then while data is read from all storage cells in the active row by the sense amplifiers, column address signals applied to the same input pins for the chip are sampled and latched in the same six address buffers, and decoded by the same decoder to select and hold a column enable line active.

REFERENCES:
patent: 3771147 (1973-11-01), Boll et al.
patent: 3936812 (1976-02-01), Cox et al.
patent: 3940747 (1976-02-01), Kuo et al.
patent: 3969706 (1976-07-01), Proebsting et al.
patent: 4004284 (1977-01-01), Heeren
Stein et al, Storage Array and Sense/Refresh Circuit for Single-Transistor Memory Cells, IEEE J. of Solid-State Circuits, vol. SC-7, No. 5, 10/72, pp. 336-340.

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