Mosfet integrated delay line for digital signals

Details Mosfet integrated delay line for digital signals Mosfet integrated delay line for digital signals

1987-03-09

1989-02-21

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307606, 307451, 307469, H03K 1728, H03K 1900

Patent

active

048068047

ABSTRACT:
For continuously adjusting the time delay of this delay line the latter is designed to consist of stages (l, n) which are of the same kind, and contains per stage a conventional CMOS inverter to which, on the P-channel transistor side, a P-channel constant-current transistor and, on the N-channel transistor side, an N-channel constant-current transistor is connected in series. The N-channel constant-current transistors form part of an N-channel multiple current mirror, and likewise, the P-channel constant-current transistors form part of a P-channel multiple current mirror. Among each other all transistors of the two current mirrors are capable of conducting currents which are equal in terms of magnitude and equal in relation to an adjustable reference current.

REFERENCES:
patent: 4260959 (1981-04-01), Allgood
patent: 4387349 (1983-06-01), Rapp
patent: 4438352 (1984-03-01), Mardkha
patent: 4489342 (1984-12-01), Gollinger et al.
patent: 4565934 (1986-01-01), Southerland, Jr.
patent: 4613772 (1986-09-01), Young
patent: 4712021 (1987-12-01), Gollinger

Affiliated with

Also associated with

Rating

Mosfet integrated delay line for digital signals does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Mosfet integrated delay line for digital signals, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Mosfet integrated delay line for digital signals will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1524526