MOSFET Integrated delay circuit for digital signals and its use

Details MOSFET Integrated delay circuit for digital signals and its use MOSFET Integrated delay circuit for digital signals and its use

1982-02-16

1984-12-18

Chin, Tommy P.

Facsimile and static presentation processing

Static presentation processing

Attribute control

358 18, 307605, H04N 593

Patent

active

044893426

ABSTRACT:
To adjust time delays in equidistant steps, an inverter chain is provided with an even number of static inverters of identical topology. The output of one of the even-numbered inverters is connected to the signal output via a selector switch. During suitable frequency-measuring periods, an odd number of inverters is connected to form a ring by directly coupling the output of an odd-numbered inverter to the input of the first, and a digital measuring arrangement determines the time delay of the ring-connected portion from the frequency of the ring's self-excited oscillation. The output signal of the measuring arrangement is used to adjust the time delay of the inverter chain.

REFERENCES:
patent: 4178607 (1979-12-01), Mikado
patent: 4268852 (1981-05-01), Nakamura
patent: 4268853 (1981-05-01), Nakamura

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