MOSFET having buried shield plate for reduced gate/drain capacit

Details MOSFET having buried shield plate for reduced gate/drain capacit MOSFET having buried shield plate for reduced gate/drain capacit

1998-04-22

2000-08-22

Fahmy, Wael

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Field plate electrode

438286, 438283, 438183, 438197, 257340, 257386, H01L 2176, H01L 21336, H01L 218234, H01L 2976, H01L 2994

Patent

active

061071609

ABSTRACT:
Gate to drain capacitance in a lateral DMOS and vertical DMOS field effect transistor is minimized by providing a conductive shield plate under the gate and between the gate and the drain of the transistor. In operation, the shield plate is preferably connected to a DC voltage potential and coupled to AC ground for RF power applications. The shield plate is readily fabricated in a conventional polysilicon gate process by adding one additional polysilicon deposition (or other suitable material), one additional mask, and one additional etch step. The shield plate can include a raised portion which provides lateral capacitive isolation between the gate and the drain. Alternatively, a shield contact can be provided above the shield plate and between the gate and drain to provide lateral isolation.

REFERENCES:
patent: 5243234 (1993-09-01), Lin et al.

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