MOSFET fabrication process with lightly-doped drain using local

Details MOSFET fabrication process with lightly-doped drain using local MOSFET fabrication process with lightly-doped drain using local

1991-06-06

1992-03-31

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 69, 437233, 357 233, H01L 21336

Patent

active

051008203

ABSTRACT:
A gate oxide layer, a polysilicon layer, and an oxidation-resistant layer are formed in sequence on a semiconductor substrate, the oxidation-resistant layer is patterned, then high-pressure oxidation is performed, oxidizing at least part of the polysilicon layer not covered by the oxidation-resistant layer and leaving, under the oxidation-resistant layer, a polysilicon gate electrode with tapered sides. The oxidized portions of the polysilicon layer are removed and two ion implantation steps are carried out with different accelerating energies and impurity doses, one step creating heavily-doped source and drain areas, the other step creating lightly-doped offset layers. The lightly-doped offset layers are at least partially located under the tapered sides of the gate electrode.

REFERENCES:
patent: Re32800 (1988-12-01), Han et al.
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patent: 4503601 (1985-03-01), Chiao
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patent: 4786609 (1988-11-01), Chen
R. Izawa et al.; "The Impact of Gate-Drain Overlapped LDD (Gold) for Deep Submicron VLSI'S"; 1987 IEDM Technical Digest, pp. 38-41.

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