MOSFET Convolved logic

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307242, 307243, 307463, 307468, 324 73R, H03K 19003, H03K 19017, H03K 19173, G01R 1512

Patent

active

043564135

ABSTRACT:
A generic FET logic circuit topology is disclosed which employs non-thresholded path routing to eliminate logic transition times in the critical data path. Non-threshold logic performs logic operations with non-inverting unity gain OR and AND functions. The propagation time through the logic matrix is therefore similar to the delay through a chain of linear amplifiers, as contrasted to an algebraic accumulation of delays with conventional logic techniques. This results in an N-factor improvement in the power-delay product over conventional techniques, where N is the number of logic operations being performed.

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patent: 4233524 (1980-11-01), Burdick
McKenny, "Depletion-Mode Devices Hike Speed of MOS Random Access Memory", Electronics; pp. 80-85; 2-1971.

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