MOSFET buffer for TTL logic input and method of operation

Details MOSFET buffer for TTL logic input and method of operation MOSFET buffer for TTL logic input and method of operation

1975-12-29

1978-06-20

Anagnos, Larry N.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307264, 307DIG1, 307DIG4, 365230, H03K 520, H03K 518, G11C 800

Patent

active

040964027

ABSTRACT:
An input buffer for MOSFET integrated circuit for receiving low level voltage signals even below the threshold voltages of the transistors comprising the circuit is described. A reference voltage between two logic levels of the input voltage, such as TTL logic signals of 0.8 volts and 1.8 volts, is trapped on a reference storage node and the logic input voltage is trapped on a data input storage node. The two trapped voltages are then capacitively boosted by the same voltage to a level well above the transistor threshold voltage so that the differences in the voltage levels can be amplified, and the logic signal latched up by conventional circuitry. The voltage levels need be only momentarily boosted above the threshold level. The circuit includes a system for protecting against input voltage undershoot which includes another capacitive input storage node with a first trapping transistor between the logic input to the circuit and the second storage node and a second trapping transistor between the second storage node and the data input storage node. This prevents any degradation of voltage level on the data storage node should the input logic level momentarily be pulled more than one threshold below the level, typically ground, to which the gates of the transistors are taken after the voltage is trapped on the data node.

REFERENCES:
patent: 3729723 (1973-04-01), Yamamoto
patent: 3760381 (1973-09-01), Yao
patent: 3789239 (1974-01-01), Heeren
patent: 3882326 (1975-05-01), Kruggel
patent: 3891977 (1975-06-01), Amelio et al.
patent: 3892984 (1975-07-01), Stein
patent: 3906464 (1975-09-01), Lattin
patent: 3959781 (1976-05-01), Mehta et al.

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