MOSFET-based power supply clamps for electrostatic discharge pro

Details MOSFET-based power supply clamps for electrostatic discharge pro MOSFET-based power supply clamps for electrostatic discharge pro

1997-03-24

1999-05-25

Gaffin, Jeffrey

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

361 56, 361 58, 361118, H02H 300

Patent

active

059074647

ABSTRACT:
Electrostatic discharge protection circuits adapted for use in low voltage CMOS processes have at least one PFET in the primary charge conduction path, and timer circuits configured to enable the primary conduction path during ESD events and to disable the primary conduction path during steady state conditions.
In a further aspect of the present invention, bias circuits for maintaining steady state gate voltages below the dielectric breakdown level are included.
In a still further aspect of the present invention a bridge circuit couples a first power supply node to a second power supply node, where the second power supply node is coupled to an ESD protection circuit.

REFERENCES:
patent: 5400202 (1995-03-01), Metz et al.
patent: 5530612 (1996-06-01), Maloney
patent: 5543650 (1996-08-01), Au et al.
patent: 5654862 (1997-08-01), Worley et al.
E.R. Worley et al, Rockwell Telecommunications; Sub-Micron Chip ESD Protection Schemes Which Avoid Avalanching Junctions; EOS/ESD Symposium 95-13-95-20; pp. 1.2.1-1.2.8.
Merrill, Issaq, National Semiconductor Fairchild Research Center; ESD Design Methodology; EOS/ESD Symposium 93-233-93-237; pp. 5B.5.1-5B.5.5.

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