Television – Camera – system and detail – Solid-state image sensor
Reexamination Certificate
1998-02-11
2001-10-09
Garber, Wendy R. (Department: 2712)
Television
Camera, system and detail
Solid-state image sensor
C348S302000, C348S307000, C348S308000, C257S291000, C257S292000
Reexamination Certificate
active
06300978
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging apparatus using an amplification-type MOS sensor for amplifying signal charges within cells.
Recently, compact video cameras and high-resolution, high-vision solid-state imaging apparatuses have been developed. Strong demands have arisen for not only compact cameras and solid-state imaging apparatuses but also low-power-consumption, low-voltage solid-state imaging apparatuses as portable cameras and personal computer cameras.
As the chip size of a solid-state imaging apparatus decreases, however, the amount of signal charge to be processed decreases due to micropatterning. As a result, the dynamic range of the solid-state imaging apparatus narrows, and hence a clear, high-resolution video cannot be obtained. In addition, since many power supply voltages having two, three, or more values are used, a simple system cannot be coped with in terms of camera system configuration and handling. That is, for application to portable cameras and personal computer cameras, a solid-state imaging apparatus which attains a high S/N ratio and uses a single power supply, and also attains reductions in power consumption and voltage is required.
To solve this problem, several amplification-type solid-state imaging apparatuses using transistors have been proposed. These solid-state imaging apparatuses are designed to cause transistors to amplify signals detected by photodiodes in the respective cells, and are characterized by having a high sensitivity.
FIG. 1
is a circuit diagram showing the arrangement of a conventional solid-state imaging apparatus using an amplification-type MOS sensor. Unit cells P
0
-i-j corresponding to pixels are arranged in the form of a two-dimensional matrix. Although
FIG. 1
shows only a 3×3 matrix, the actual apparatus has several thousand cells×several thousand cells. Reference symbol i denotes a variable in the horizontal (row) direction; and j, a variable in the vertical (column) direction. Each unit cell P
0
-i-j is constituted by a photodiode
1
-i-j for detecting incident light, an amplification transistor
2
-i-j having a gate to which the cathode of the photodiode
1
-i-j is connected and designed to amplify the detection signal, a vertical selection transistor
3
-i-j connected to the drain of the amplification transistor
2
-i-j to select a horizontal line for reading out the signal, and a reset transistor
4
-i-j connected to the cathode of the photodiode
1
-i-j to reset the signal charge. The source of the vertical selection transistor
3
-i-j and the source of the reset transistor
4
-i-j are commonly connected to a drain voltage terminal.
Vertical address lines
6
-
1
,
6
-
2
, . . . horizontally extending from a vertical address circuit
5
are connected to the gates of vertical selection transistors
3
-
1
-
1
, . . . of the unit cells in the respective rows to determine horizontal lines for reading out signals. Similarly, reset lines
7
-
1
,
7
-
2
, . . . horizontally extending from the vertical address circuit
5
are connected to the gates of reset transistors
4
-
1
-
1
, . . . in the respective rows.
The sources of amplification transistors
2
-
1
-
1
, . . . of the unit cells in the respective rows are connected to vertical signal lines
8
-
1
,
8
-
2
, . . . arranged in the column direction. Each of load transistors
9
-
1
,
9
-
2
, . . . is connected to one end of a corresponding one of the vertical signal lines
8
-
1
,
8
-
2
, . . . . A signal output terminal (horizontal signal line)
15
is connected to the other end of each of the vertical signal lines
8
-
1
,
8
-
2
, . . . through horizontal selection transistors
12
-
1
,
12
-
2
, . . . which are driven by horizontal address pulses output from a horizontal address circuit
13
.
FIG. 2
is a timing chart showing the operation of this device. When a high-level address pulse is applied to the vertical address line
6
-
1
, only the vertical selection transistors
3
in this line are turned on. As a result, a source follower circuit is constituted by the amplification transistor
2
and the load transistor
9
in this line.
With this operation, the gate voltage of the amplification transistor
2
, i.e., almost the same voltage as that of the photodiode
1
, appears on the vertical signal line
8
.
Horizontal address pulses are sequentially applied from the horizontal address circuit
13
to the horizontal selection transistors
12
-
1
,
12
-
2
, . . . to sequentially output signals corresponding to lines (rows) from the signal output terminal
15
. When the signal corresponding to one line is completely read out, a high-level reset pulse is applied to the reset line
7
-
1
to turn on the reset transistor
4
in this line so as to reset the signal charge.
By sequentially performing this operation for the subsequent lines, all the signals in the two-dimensional matrix can be read out. In this case, a voltage corresponding to almost the same change in the potential of the photodiode
1
appears on the vertical signal line
8
. If the capacitances of the photodiode
1
and the vertical signal line
8
are respectively represented by Cs and Cv, the signal charge is amplified Cv/Cs times. In general, Cv is much larger than Cs.
In a solid-state imaging apparatus using an amplification-type MOS sensor of this type, the following problem is posed. Since variations in the threshold voltages of the amplification transistors
64
are superimposed on signals, even if the potentials of the photodiodes
62
are the same, the output signals vary. For this reason, when a picked-up image is reproduced, two-dimensional noise (called fixed pattern noise because the noise is fixed to a specific place) due to the threshold variations of the amplification transistors
64
is generated.
As described above, in a solid-state imaging apparatus using an amplification-type MOS sensor, there is a problem in which the fixed pattern noise due to the threshold variations of the amplification transistors appears in the picked-up image.
It is an object of the present invention to provide an MOS-type solid-state imaging apparatus which suppresses the two-dimensional fixed pattern noise due to the threshold variation of the amplification transistors.
BRIEF SUMMARY OF THE INVENTION
According to the present invention, there is provided an MOS-type solid-state imaging apparatus comprising unit cells arranged in an array; means for selecting one of the unit cells, wherein each of the unit cells comprises a photoelectric converter; an amplification transistor having a gate to which the photoelectric converter is connected and for amplifying an output signal from the photoelectric converter and output an amplified signal; a selection transistor having a gate to which the selecting means is connected and for selectively turning on the amplification transistor; and a reset transistor connected between a connection point between the amplification transistor and the selection transistor and a gate of the amplification transistor for selectively resetting the gate of the amplification transistor.
According to the present invention, there is provided another MOS-type solid-state imaging apparatus comprising an imaging region having unit cells arranged in a two-dimensional matrix, each unit cell being constituted by a photodiode, an amplification transistor having a gate to which an output from the photodiode is input, a vertical selection transistor connected in series with the amplification transistor, and a reset transistor connected between the drain and gate of the amplification transistor to discharge the signal from the photodiode; vertical address lines connected to gates of the vertical selection transistors and arranged in a row direction; a vertical address circuit for driving the vertical address lines; vertical signal lines arranged in a column direction in which currents are read out from the amplification transistors; load transistors each connected to one end of a corresponding one of the vertical signal lines; horizon
Matsunaga Yoshiyuki
Miura Hiroki
Nakamura Nobuo
Ohsawa Shinji
Yamashita Hirofumi
Garber Wendy R.
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Tillery Rashawn N.
LandOfFree
MOS-type solid-state imaging apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MOS-type solid-state imaging apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS-type solid-state imaging apparatus will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2605952