MOS type semiconductor integrated circuit device

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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Reexamination Certificate

active

11251824

ABSTRACT:
A plurality of MOS type circuits is provided, and are connected in a multistage manner. A first transistor is inserted between a power source voltage VDD and a power supply node of each of MOS type circuits at an odd numbered stage. A second transistor is inserted between the power source voltage VDD and a power supply node of each of MOS type circuits at an even numbered stage. When the plurality of MOS type circuits are established in a standby state, a control circuit first controls to make a second transistor conductive, and then make a first transistor conductive when the plurality of MOS type circuits, each of which is established in a standby state, are recovered from the standby state to an active state.

REFERENCES:
patent: 6049245 (2000-04-01), Son et al.
patent: 6118328 (2000-09-01), Morikawa
patent: 6552596 (2003-04-01), Cowles et al.
patent: 6759873 (2004-07-01), Kang et al.
patent: 2006/0133177 (2006-06-01), Kushida et al.
patent: 2002-64150 (2002-02-01), None
Koji Nii, et al. “A 90 nm Low Power 32K-Byte Embedded SRAM with Gate Leakage Suppression Circuit for Mobile Applications”, 2003 Symposium on VLSI Circuits Digest of Technical Papers, pp. 247-250.
Kenichi Osada, et al. “16.7fA/cell Tunnel-Leakage-Suppressed 16Mb SRAM for Handling Cosmic-Ray-Induced Multi-Errors”, 2003 IEEE International Solid-State Circuits Conference, 10 Pages.

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