MOS-type semiconductor integrated circuit

Details MOS-type semiconductor integrated circuit MOS-type semiconductor integrated circuit

2002-09-05

2004-03-30

Tokar, Michael (Department: 2819)

Induced nuclear reactions: processes, systems, and elements

Nuclear fusion

Including accelerating particles into a stationary or static...

C326S017000, C326S112000, C326S119000

Reexamination Certificate

active

06714615

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an MOS-type semiconductor integrated circuit including a CMOS transistor circuit which is adapted to an interface between circuit areas of different supply voltages.
In general, a circuit at the preceding stage of an MOS transistor switch circuit, which is constructed into a circuit interface, comprises a logic circuit such as an inverter, an NAND circuit or an NOR circuit.
FIG. 1
is a circuit diagram showing a combination of an inverter IV
6
and an MOS transistor switch SW
6
according to prior art. This circuit comprises a total of four elements, namely, two P-channel MOS transistors P
1
and P
2
and two N-channel MOS transistors N
1
and N
2
.
The inverter IV
6
has the transistors P
1
and N
1
connected in series between a supply voltage VCC and a ground potential VSS, with the gates of both transistors being connected together to an input node IN. The drains of both transistors are connected together to an output node S.
The MOS transistor switch SW
6
has the transistors P
2
and N
2
connected with their current paths in parallel to each other. The gates of both transistors P
2
and N
2
are respectively supplied with complementary clock signals CLK and CLKb in which when one of which becomes a high level “H”, the other one has a low level “L”. One end of the node of the parallel connection is connected to the output node S and the other end of the parallel connection is connected to an output node OUT for driving a capacitive load C
0
.
In this circuit, therefore, when the clock signal CLK is at “L” (low level) and the clock signal CLKb is at “H” (high level), the nodes S and OUT are electrically connected together, so that the input level from the previous stage is output as it is. When the clock signal CLK is at “H” and the clock signal CLKb is at “L”, the nodes S and OUT are electrically disconnected from each other, so that there is a high impedance state between both nodes.
In such an ordinary combination of an inverter and an MOS transistor switch, when the MOS transistor switch is at a high impedance state, the supply voltage VCC is applied between the source and drain of each transistor N
2
or P
2
depending on the input from the preceding stage or the voltage status on the output side.
If the input to the input node IN has the “H” level (VCC level) and the input clock signal CLK/CLKb is “L”/“H” in the initial state, for example, the output node S becomes “L” so that an output of the “L” level is output from the output node OUT. At this time, the voltage of VCC is applied between the source and drain of the transistor P
1
. When the level of the input to the input node IN changes to “L” from “H” after the level of the clock signal CLK/CLKb changes to “H”/“L” from “L”/“H”, the voltage of VCC is applied between the source and drain of each of the transistors N
1
, N
2
and P
2
.
As the miniaturization of transistors that are incorporated into a semiconductor device progresses, the number of circuit portions which are driven by the internally dropped voltage as the supply voltage increases. In this respect, more attempts are being made to design transistors on the premise of the use of the internally dropped voltage. Such a design process often guarantees the reliability of transistors only in the range of the internally dropped voltage.
That is, an ordinary circuit structure will be applied with too high voltage to the transistors in the circuit area that generates an internally dropped voltage from an external supply voltage, the external interface and the portion which cannot use the dropped voltage as its supply voltage from the viewpoint of the circuit structure, which may deteriorate the transistors. Some kind of voltage buffer means is therefore essential to deal with this problem.
Even in the circuit combination of the inverter and MOS transistor switch as shown in
FIG. 1
, therefore, the external supply voltage may be applied directly between the source and drain of each transistor in some cases. To make the circuit operable on the external supply voltage therefore demands some kind of countermeasures.
Generally speaking, an MOS transistor is deteriorated when the transistor is turned on with the supply voltage applied between its source and drain, thus causing the current to flow through the transistor. This case is equivalent to the switching of the transistor to the ON state from the OFF state.
As apparent from the above, the miniaturization of transistors increases the number of circuit portions which use the internally dropped voltage as the supply voltage and guarantees the reliability of transistors only in the range of the internally dropped voltage. Such a transistor circuit inevitably includes the circuit area that generates an internally dropped voltage from an external supply voltage, the external interface and a portion which cannot uses the dropped voltage as its supply voltage from the viewpoint of the circuit structure.
It is therefore necessary to add a circuit serving as voltage buffer means in such circuit portions. The addition of such a voltage buffer circuit inevitably results in an increase in the pattern area and a reduction in signal transmission speed. Some attempts should therefore be made to suppress this inconvenience.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide an MOS-type semiconductor integrated circuit which decreases the maximum voltage to be applied between the source and drain of each MOS transistor while minimizing an increase in the number of elements in an MOS transistor switch circuit and a reduction in signal transmission speed.
To achieve the above object, according to one aspect of this invention, there is provided an MOS-type semiconductor integrated circuit comprising a switch circuit including a logic circuit operable on a voltage between a predetermined high-potential supply voltage and a low-potential supply voltage and a first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity for controlling transfer of an output of the logic circuit with complementary signals; an output node of the logic circuit being separated into a first node to be connected to a path including the first MOS transistor and a second node to be connected to a path including the second MOS transistor; and a current path comprising one or more MOS transistors and inserted between the first node and the second node, and a current path comprising an MOS transistor of the same conductivity as that of at least one of the path including the first MOS transistor and the path including the second MOS transistor and provided between the at least one of the path including the first MOS transistor and the path including the second MOS transistor and an output node of the switch circuit.
According to this invention, a current path including a minimum number of MOS transistors is provided where needed with respect to a transistor whose breakdown voltage is lower than the high-potential supply voltage, thereby making the voltage applied to that transistor lower than the high-potential supply voltage.


REFERENCES:
patent: 4609836 (1986-09-01), Koike
patent: 5541529 (1996-07-01), Mashiko et al.

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