MOS transistor with serrated gate structures

Details MOS transistor with serrated gate structures MOS transistor with serrated gate structures

2006-04-04

2006-04-04

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

C257S700000, C257S758000, C438S618000, C438S622000

Reexamination Certificate

active

07023032

ABSTRACT:
A digital power supply system provides a supply voltage to semiconductor circuits. The power supply system utilizes a pulse width modulator to output a signal into a LC filter that generates a DC supply voltage. The width of the pulses output by the pulse width modulator are defined by an encoder that generates width information in response to a propagation delay detector that measures the propagation delay of a first clock signal when clocked by a second clock signal.

REFERENCES:
patent: 4247916 (1981-01-01), Erb
patent: 4462041 (1984-07-01), Glenn
patent: 4725747 (1988-02-01), Stein et al.
patent: 5793068 (1998-08-01), Mahant-Shetti
patent: 6686300 (2004-02-01), Mehrotra et al.
Dragan Maksimovic, Bruno Kranzen, Sandeep Dhar and Ravindra Ambatipudi, U.S. Appl. No. 10/053,226, filed Jan. 19, 2002, entitled “An Adaptive Voltage Scaling Digital Processing Component and Method of Operating the Same”.
Bruno Kranzen and Dragan Maksimovic, U.S. Appl. No. 10/053,227, filed Jan. 19, 2002, entitled “Adaptive Voltage Scaling Clock Generator for Use in a Digital Processing Component and Method of Operating the Same”.
Dragan Maksimovic and Sandeep Dhar, U.S. Appl. No. 10/053,858, filed Jan. 19, 2002, entitled “System for Adjusting a Power Supply Level of a Digital Processing Component and Method of Operating the Same”.
Dragan Maksimovic, Ravindra Ambatipudi, Sandeep Dhar and Bruno Krazen, U.S. Appl. No. 10/053,228, filed Jan. 19, 2002, entitled “An Adaptive Voltage Scaling Power Supply for Use in a Digital Processing Component and Method of Operating the Same”.
James T. Doyle and Dragan Maksimovic, U.S. Appl. No. 10/106,428, filed Mar. 26, 2002, entitled “Method and System for Minimizing Power Consumption in Mobile Devices Using Cooperative Adaptive Voltage and Threshold Scaling”.
Dragan Maksimovic and James Thomas Doyle, U.S. Appl. No. 10/166,822, filed Jun. 10, 2002, entitled “Serial Digital Communication Superimposed on a Digital Signal Over a Single Wire”.
Dragan Maksimovic and Sandeep Dhar, U.S. Appl. No. 10/236,482, filed Sep. 6, 2002, entitled “Method and System for Providing Self-Calibration for Adaptively Adjusting a Power Supply Voltage in a Digital Processing System”.
Mark F. Rives, U.S. Appl. No. 10/246,971, filed Sep. 19, 2002, entitled “Power Supply System and Method that Utilizes an Open Loop Power Supply Control”.
Jim Doyle and Bill Broach, Small Gains in Power Efficiency Now, Bigger Gains Tomorrow [online]. Jul. 9, 2002 [retrieved on Feb. 1, 2003]. Retrieved from the Internet: <URL: http://www.commsdesign.com/design—corner/OEG20020709S0022>. pps. 1-5.
Robert W. Erickson and Dragan Maksimovic,Fundamentals of Power Electronics,Second Edition, Kluwer Academic Publishers, 2001, pp. 333.
Krisztian Flautner, Steven Reinhardt and Trevor Mudge, Automatic Performance Setting for Dynamic Voltage Scaling, Wireless Networks, vol. 8, Issue 5, Sep. 2002, pps. 507-520, and Citation, pps. 1-3, [online]. [retrieved on Feb. 2, 2003]. Retrieved from the Internet: <URL: http://portal.acm.org/citation.cfm?id=582455.582463&coll=portal&dl=ACM&idx=J804&p...>.
Krisztian Flautner, Steven Reinhardt and Trevor Mudge, Automatic Performance Setting for Dynamic Voltage Scaling [online]. May 30, 2001, [retrieved on Feb. 2, 2003]. Retrieved from the Internet: <URL: http://www.eecs.umich.edu/˜tnm/papers/mobicom01.pdf>. pps. 1-12.
Texas Instruments, “Synchronous-Buck PWM Controller With NMOS LDO Controller”, TPS5110, SLVS025A-Apr. 2002, Revised Jun. 2002.
Joonho Gil, Minkyu Je, Jongho Lee and Hyungcheol Shin, “A High Speed and Low Power SOI Inverter Using Active Body-Bias”, Association of Computing Machinery, ISLPED98, Monterey, CA, 1998, pps. 59-63.
Oliver Weinfurtner, Switcher Output Stages on Neptune 28 (CMOS7-5), Neptune 28 Output Stage Results, Sep. 24, 2001, pps. 1-8.
Intel XScale Core, Developer's Manual, Dec. 2000, [online], [retrieved on Feb. 2, 2003]. Retrieved from the Internet: <URL: http://developer.intel.com/design/intelxscale/27347301.pdf>. pps. 1-1 through B-1.
U.S. Appl. No. 10/053,858, filed Jan. 19, 2002, Maksimovic et al.
U.S. Appl. No. 10/106,428, filed Mar. 26, 2002, Doyle et al.

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