MOS transistor with good hot carrier resistance and low interfac

Details MOS transistor with good hot carrier resistance and low interfac MOS transistor with good hot carrier resistance and low interfac

1996-02-15

1998-08-11

Crane, Sara W.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257751, 257763, 257637, H01L 2348, H01L 2352, H01L 2940

Patent

active

057931100

ABSTRACT:
After a MOS transistor having a gate electrode layer is formed on the surface of a semiconductor substrate, a first interlayer insulating film and a moisture blocking film are sequentially formed. After necessary contact holes are formed in the films, a first wiring layer is deposited and patterned together with the underlying blocking film, to form wiring layers for the connection to the transistor regions and a moisture blocking pattern covering the gate electrode layer. The first wiring layer includes a lowest Ti layer, Al alloy layer, and other layers. After a second interlayer insulating film is formed covering the first wiring layers, a second wiring layer is formed on the second interlayer insulating film. The second interlayer insulating film contains a spin-on-glass film which contains moisture. The wiring material layer prevents diffusion of moisture from the second interlayer insulating film to the electrode layer, and the moisture blocking film prevents the absorption and store of moisture related species (H.sub.2 O, OH.sup.-, H.sup.+) by the Ti layer of the wiring material layer.

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