MOS transistor with an integrated protection zener diode

Details MOS transistor with an integrated protection zener diode MOS transistor with an integrated protection zener diode

1992-11-19

1994-10-18

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Device protection

257175, 257355, 257373, 257547, 257603, H01L 2702

Patent

active

053571266

ABSTRACT:
A MOS transistor is formed in a first low-doped P-type retion coating a second more highly doped P-type region. The transistor comprises an N-type drain region, an N-type source region, and a region contacting the for region. The drain, cource and contacting regions are formed at the surface of the first region. The source and contacting regions are interconnected. An N-type highly doped region extends from the drain region through the first low-doped P-type region to the second more highly doped P-type region.

REFERENCES:
patent: 4862233 (1989-08-01), Matsushita et al.
patent: 5008723 (1992-04-01), van der Have
patent: 5103425 (1992-04-01), Kuo et al.
Patent Abstracts of Japan, vol. 8, No. 261.
Patent Abstracts of Japan, vol. 9, No. 136.
Electrical Overstress/Electrostatic Discharge Symposium Proceedings, 1984, Philadelphia, Pa., USA, pp. 202-209, "A CMOS VLSI ESO Input Protection Device, DIFIDW", Lin Chong Ming, et al., p. 203.

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