MOS transistor with a charge induced drain extension

Fishing – trapping – and vermin destroying

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437 24, 357 233, H01L 21336

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active

051089408

ABSTRACT:
A process is taught which provides very shallow conductive regions in a semiconductor material by the formation of a fixed charge placed in an overlying dielectric layer which induces an inversion region in the underlying semiconductor. The inversion region so formed is used as a MOSFET drain extension between a drain contact region and the channel located beneath the gate region. The conductivity of the induced inversion region is controlled by the concentration of the ionic charge present in the dielectric layer.

REFERENCES:
patent: 3328210 (1967-06-01), McCaldin
patent: 3442721 (1969-05-01), McCaldin et al.
patent: 3607449 (1971-09-01), Takashi et al.
patent: 3657614 (1972-04-01), Cricchi
patent: 3956025 (1976-05-01), Statz et al.
patent: 3972059 (1976-07-01), DiStefano
patent: 3983574 (1976-09-01), Statz
patent: 4043024 (1977-08-01), Iwamatsu
patent: 4047974 (1977-09-01), Harari
patent: 4048350 (1977-09-01), Glang et al.
patent: 4258077 (1981-03-01), Mori et al.
patent: 4306352 (1981-12-01), Schrader
patent: 4391032 (1983-07-01), Schulte
patent: 4468574 (1984-08-01), Engeler et al.
patent: 4714519 (1987-12-01), Pfiester
patent: 4764477 (1988-08-01), Chang et al.
patent: 4994869 (1991-02-01), Matloubian et al.
Sze, Semiconductor Devices, 1985, pp. 197-200.
Eric Demoulin et al., "Process Statistics of Submicron MOSFETs" IEEE, (1979), pp. 34-37.
Eiji Takeda et al., "Device Performance Degradation Due to Hot-Carrier Injection at Energies Below the Si--SiO.sub.2 Energy Barrier," IEEE (1983), pp. 396-399.
T. Shibata et al., "An Optimally Designed Process for Submicron MOSFETs" (1981), pp. 647-650.
Seiki Ogura et al., "Elimination of Hot Electron Gate Current by the Lightly Doped Drain-Source Structure," IEEE, (1981), pp. 651-654.
Nakahara et al., "Relief of Hot Carrier Constraint on Submicron CMOS Services by Use of a Buried Channel Structure," IEEE, (1985), pp. 238-241.
Yamaguchi, "Process and Device Design of a 1000-Volt MOS IC," IEEE (1981), pp. 255-258.
E. H. Stupp et al., "Low Specific On-Resistance 400 V LDMOST", IEEE (1981), pp. 426-428.
E. H. Snow et al., "Ion Transport Phenomena in Insulating Films," J. Appl. Phys., (1975) 36:1664-1673.
Hino et al., "Neutralizatio of Mobil Ions in the SiO.sub.2 Film of MOS Structures" J. Appl. Phys., (1979), 50:4879-4882.
Eitan et al., "Surface Conduction in Short-Channel MOS Devices as a Limitation to VLSI Scaling," IEEE, (1982), 29:254-266.
Dennard et al., "Design of Ion-Implanted MOSFETs with Very Small Physical Dimensions," IEEE, (1974), 9:256-268.
Merckel, "A Simple Model of the Threshold Voltage of Short and Narrow Channel MOSFETs," Solid State Electronics, (1980), 23:1707-1213.
Yau, "A Simple Theory to Predict the Threshold Voltage of Short-Channel IGFETs," Solid State Electronics (1974), 17:1059-1063.

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