Electricity: power supply or regulation systems – Self-regulating – Using a three or more terminal semiconductive device as the...
Reexamination Certificate
2000-06-13
2001-04-03
Han, Jessica (Department: 2838)
Electricity: power supply or regulation systems
Self-regulating
Using a three or more terminal semiconductive device as the...
C327S540000, C327S542000
Reexamination Certificate
active
06211660
ABSTRACT:
This invention relates to MOS (metal-oxide-semiconductor field effect) transistor output circuits using PMOS transistors. The invention is particularly applicable but is not limited to, and is described below in the context of, a signal voltage converter for converting between signal voltages in MOS circuits which have different supply voltages. MOS circuits include CMOS (complementary MOS) and BCMOS (bipolar and CMOS) circuits which may be used for handling signals at very high frequencies, for example of the order of 5 GHz.
BACKGROUND
It is known to provide for example a BCMOS circuit with supply voltages of +5, 0, and −5 volts, in which signal voltages are between 0 and −5 volts, being close to 0 volts and −5 volts to represent logic levels 1 and 0 respectively. In order to couple such a signal to another (e.g. integrated circuit) device which operates with supply voltages of +5 and 0 volts, it is necessary to convert the signal to voltage levels between +5 and 0 volts, in particular so that the signal logic levels are represented by typical CMOS voltage levels close to +5 volts and 0 volts to represent logic levels 1 and 0 respectively.
This signal conversion involves a shifting of the signal voltage by +5 volts for each logic level, and while this is simple in concept, in practice it presents challenges which arise from voltage constraints and characteristics of the technology that may be used for producing the integrated circuits, in conjunction with needs to maintain a desired frequency response or signal bandwidth and to avoid distortion of signal timing.
As is well known, a CMOS output circuit having supply voltages of +5 and 0 volts comprises a PMOS transistor for pulling the signal voltage up so that it is close to +5 volts and an NMOS transistor for pulling the signal voltage down so that it is close to 0 volts. Such an output circuit determines the typical CMOS signal voltages for logic 1 and 0 levels for which input circuits of CMOS devices are designed. However, for example in a BCMOS integrated circuit having supply voltages of +5, 0, and −5 volts, while it is practical to provide a PMOS transistor which is insulated from the substrate so that it can operate at independent voltage levels, an NMOS transistor can only practically be provided if its source is connected to the substrate, which is at the negative voltage of −5 volts. Consequently, it is not practical to provide an output circuit with an NMOS transistor for pulling down the signal to the level of close to 0 volts as is required.
In the prior art, it is known to address this difficulty by instead using an NPN bipolar transistor of the BCMOS integrated circuit for pulling down the signal to the logic 0 level of close to 0 volts. However, such bipolar transistors have collector-emitter voltages which may be greater than a maximum required logic 0 signal voltage level unless the transistor is driven into saturation, which limits high frequency operation. In addition, typical capacitive loading of the output produces different time constants for different signal transitions (logic 0 to 1 and logic 1 to 0 transitions) due to the different characteristics of the pull-up and pull-down transistors. This results in a distortion of signal timing. For example, in a signal voltage converter an input signal with a 50% duty cycle will produce a voltage-converted output signal with a duty cycle that is not 50%.
It is also necessary, in any such signal voltage converter or other circuit implemented using a technology for which voltage limits between terminals of the transistors are less than the total supply voltage, to ensure that these limits are not generally exceeded in operation of the circuit. For example, such a voltage limit may be a maximum of 6 volts between any two terminals of the same transistor, compared with a total supply voltage of 10 volts for supplies of +5 volts and −5 volts.
A need therefore exists to provide an improved MOS transistor output circuit, and an improved signal voltage converter using such an output circuit.
SUMMARY OF THE INVENTION
One aspect of this invention provides a MOS transistor output circuit having terminals for relatively positive, zero, and negative supply voltages, comprising: a first PMOS transistor having a source connected to the positive supply voltage, a gate, and a drain connected to an output; a second PMOS transistor having a source connected to the output, a gate, and a drain connected to the zero supply voltage; at least one current mirror arrangement comprising at least a third PMOS transistor having a source connected to the positive supply voltage, a gate, and a drain, the at least one current mirror arrangement being responsive to an input signal for controlling the first and third PMOS transistors via their gates to be simultaneously conductive and simultaneously non-conductive for respective logic levels of the input signal; a fourth PMOS transistor having a source coupled to the drain of the third PMOS transistor, a gate coupled to the zero voltage supply, and a drain coupled to the gate of the second PMOS transistor; and a clamp circuit coupled to the gate of the second PMOS transistor and responsive to the input signal for supplying a relatively positive or negative voltage to the gate of the second PMOS transistor, to render the second PMOS transistor respectively non-conductive or conductive, when the first and third PMOS transistors are respectively conductive and non-conductive.
In particular, the input signal may have voltages between the zero and negative supply voltages, the output circuit further comprising at least one level shifter responsive to the input signal for conducting an input current of said at least one current mirror arrangement, the at least one level shifter comprising an NPN bipolar transistor having a base coupled to the zero supply voltage, an emitter coupled via a resistor to a signal path, and a collector coupled to the at least one current mirror arrangement.
Another aspect of the invention provides a MOS transistor signal voltage converter having relatively positive, zero, and negative supply voltages for converting an input signal having logic levels represented by voltages at about the zero and negative supply voltages to an output signal having logic levels represented by voltages at about the positive and zero supply voltages, the converter comprising: a first PMOS transistor having a source connected to the positive supply voltage, a gate, and a drain connected to an output for the output signal; a second PMOS transistor having a source connected to the output, a gate, and a drain connected to the zero supply voltage; at least one level shifter comprising an NPN bipolar transistor having a base coupled to the zero supply voltage, an emitter coupled to a signal path responsive to the input signal, and a collector; at least one current mirror arrangement coupled to the collector of the at least one level shifter and including at least a third PMOS transistor having a source connected to the positive supply voltage, a gate, and a drain, the at least one current mirror arrangement being responsive to current conducted by the transistor of the at least one level shifter to control the first and third PMOS transistors via their gates to be simultaneously conductive and simultaneously non-conductive for respective logic levels of the input signal; a fourth PMOS transistor having a source coupled to the drain of the third PMOS transistor, a gate coupled to the zero voltage supply, and a drain coupled to the gate of the second PMOS transistor; and a clamp circuit coupled to the gate of the second PMOS transistor and responsive to the input signal for controlling the second PMOS transistor to be respectively non-conductive and conductive when the first and third PMOS transistors are respectively conductive and non-conductive.
The clamp circuit can comprise a first terminal responsive to the input signal; a second terminal coupled to the gate of t
Han Jessica
Nortel Networks Limited
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