MOS transistor isolation method

Details MOS transistor isolation method MOS transistor isolation method

1991-09-30

1992-07-28

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 61, 437 69, H01L 2176, H01L 21302

Patent

active

051340895

ABSTRACT:
A series of oxide growth and etch-back operations is employed to form the isolation region of an MOS device (10). The series of operations forms an oxidation susceptible layer (14) into oxidation resistant areas (21) and oxidation susceptible areas (19) thereby confining the effects of a thermal oxidation procedure to the oxidation susceptible areas (19) of the MOS device (10). The thickness of both the oxidized (19) and non-oxidized regions (21) is reduced. Another oxidation is performed and the oxidized material (19, 21) is thinned.

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patent: 4577394 (1986-03-01), Peel
patent: 4743566 (1988-05-01), Bastiaens et al.
patent: 4847213 (1989-07-01), Pfiester
patent: 4942449 (1990-07-01), Wei et al.
patent: 5019526 (1991-05-01), Yamane et al.
patent: 5049520 (1991-09-01), Cathey

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