MOS transistor in an integrated circuit and active area...

Details MOS transistor in an integrated circuit and active area... MOS transistor in an integrated circuit and active area...

2001-03-29

2004-06-08

Thomas, Tom (Department: 2815)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S296000, C438S424000

Reexamination Certificate

active

06746935

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to integrated circuits on a semiconductor substrate including at least one component formed in an active area and more specifically to the forming of active areas surrounded with insulating areas. These insulating areas are obtained from trenches filled with an insulating material and each active area is intended for receiving a conductive layer insulated therefrom, for example a control gate of a device of transistor type. The device may be a MOS transistor formed by any known technology (MOS, CMOS, BiCMOS).
BACKGROUND OF THE INVENTION
FIG. 1
partially and schematically illustrates in a transversal cross-section view a semiconductor substrate
1
on which is formed an insulated conductive line. It is considered hereafter as a non-limiting example that this line is a gate electrode of a MOS transistor of lateral type.
In
FIG. 1
, substrate
1
includes an active area
5
delimited by an insulating area
2
. Insulating area
2
has been formed by digging trenches into the substrate, then by filling them with an insulating material, typically silicon oxide (SiO
2
). The filling is performed so that the insulating material overflows, as indicated by dotted line
6
, with respect to the level defined by the substrate, whereby insulating area
2
has a top having a substantially planar surface at a level higher than the surface of the active area
5
thus defined, this top ending in a substantially vertical edge leading to active area
5
. Such an insulating area structure
2
can be conventionally obtained in several ways, as will be discussed hereafter.
Insulating area
2
has, in contact with active area
5
, an embattling area which, due to overetchings in subsequent steps of removal of various sacrificial insulating materials, will cause a depression
7
at the periphery of active area
5
.
At the level of a gate area, a thin insulator layer
3
covers the upper surface of active area
5
as well as its peripheral portion exposed by depression
7
. Layer
3
is covered with a layer
4
of a conductive material, typically polysilicon. Conductive material
4
passes over insulating area
2
and over active area
5
, and fills depression
7
. The filling of depression
7
by the gate material has disturbing effects. Indeed, because of the curvature exhibited on the edge of active area
5
by the gate material due to this depression, the distribution of the electric field in the channel area located at the edge of insulating area
2
is disturbed, which deteriorates, as will be seen hereafter, the transistor performances.
FIG. 2
illustrates in top view a MOS transistor of lateral type. In this case,
FIG. 1
corresponds to a partial cross-section view along line A—A′, limited by an area defined by the dotted lines. Active area
5
includes a channel area, located under a control gate
4
and, on either side of the gate, source and drain regions. The gate, drain, and source contacting points are underscored by hatched regions, the location of which is indifferent to the discussion of the present invention.
Depression
7
exhibited by insulating layer
2
is located over the entire periphery P of active area
5
. The portions of periphery P underlying the gate are underscored by check patterns
8
and it can be considered that the MOS transistor of
FIG. 2
is formed of two transistors: a central transistor with normal performances, having a planar gate parallel to the surface of substrate
1
and, on either side of the central transistor, a parasitic transistor with impaired performances located along insulating layer
2
, having a non-planar gate extending over depression
7
.
FIG. 3
shows the drain-source current Ids, in logarithmic coordinates as a function of gate-source voltage Vgs. Curve C
1
corresponds to the central transistor and has a normal threshold voltage V
1
and a normal leakage current I
1
off (current Ids for Vgs=0). Curve C
2
corresponds to the parasitic transistor and has a decreased threshold voltage V
2
and an increased leakage current I
2
off. Since the resulting MOS transistor has a characteristic corresponding to the sum of curves C
1
and C
2
, its threshold voltage will also be lowered and, above all, its leakage current Ioff will be increased. This causes leakages, which are very disturbing, for example, in applications where the considered transistor belongs to a chip powered by a battery, as in portable phones, the battery being then likely to discharge more rapidly.
Further, it should be noted that the adverse effects of the parasitic transistor are all the more significant as active area
5
is narrow. Given the constant tendency of the semiconductor industry to reduce the sizes of transistors, the adverse effect of the parasitic transistor can only be enhanced, and the transistor can even stop existing if the gate width becomes to small, the resulting transistor being then only formed by the parasitic transistor.
SUMMARY OF THE INVENTION
An embodiment of the present invention provides a MOS transistor which avoids the disadvantages of prior art and has a non-impaired voltage threshold.
Another embodiment of the present invention provides a method of forming an active area in a semiconductor substrate enabling obtaining such a structure. The method forms an active area surrounded with an insulating area in a semiconductor substrate, including the steps of:
a) forming in the substrate a trench surrounding an active area;
b) filling the trench with an insulating material to form an edge extending beyond the substrate surface at the periphery of the active area;
c) forming a spacer at the periphery of said edge; and
d) implanting a dopant, whereby the implantation in the area located under the spacer is less deep than in the rest of the active area.
According to an embodiment of the present invention, the spacer has a substantially vertical edge or has a bell shape, the thickness of which thins down as the distance from said edge increases.
According to an embodiment of the present invention, the implantation step is followed by a step of removal of the spacer.
According to an embodiment of the present invention, the step of removal of the spacer is preceded or followed by a step of implantation of another active area with a dopant of another conductivity type than that of the dopant used at step d).
According to an embodiment of the present invention, a step consisting of forming, at the surface of the active area, a protective coating, is provided between the trench filling step and spacer forming step c).
According to an embodiment of the present invention, the protective coating results from the thermal growth of a thin silicon oxide layer at the surface of the substrate.
According to an embodiment of the present invention, the spacer is made of silicon nitride.
According to an embodiment of the present invention, the spacer is made of polysilicon.
An embodiment of the present invention also provides a MOS transistor including a doped channel area adjacent to an insulating area, the dopants present in the portion of the channel area in contact with the insulating layer being closer to the surface than the dopants present in the rest of the channel area.
Another embodiment of the present invention includes an integrated circuit including such a transistor and a terminal including such an integrated circuit.
Many features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.


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patent: 6022781 (2000-02-01), Noble et al.
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patent: 6235596

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