MOS transistor having increased gate-drain capacitance

Details MOS transistor having increased gate-drain capacitance MOS transistor having increased gate-drain capacitance

1993-10-21

1995-03-14

Carroll, J.

Fishing, trapping, and vermin destroying

437 30, 437 41, 437 44, 257346, 257387, H01L 21265, H01L 2906

Patent

active

053977157

ABSTRACT:
A process is described for providing a self-aligned MOS transistor having a selectable gate-drain capacitance. In a self-aligned process for forming a PMOS transistor, a polysilicon layer is etched to expose portions of an n-type substrate in which it is desired to form p+ drain regions. A deep p.sup.+ drain region is then formed in the surface of the substrate so as to have a large diffusion under the polysilicon layer. This large diffusion results in a high gate-drain capacitance. The polysilicon layer is further etched to form a gate. A self-aligned source is then formed using a separate, relatively shallow p+ diffusion. The selectable gate-drain capacitance obviates the need to form separate capacitors on the substrate to use as gate-drain capacitors.

REFERENCES:
patent: H986 (1991-11-01), Codella et al.
patent: 4154626 (1979-05-01), Joy et al.
patent: 4757032, Contiero
patent: 4837186 (1989-06-01), Ohata et al.
"Process for making very small asymmetric feed-effect transitions", IBM Technical Disclosure Bulletin, vol. 30, (Aug. 1987) pp. 1136-1137.
"High-performance FET deow structure and method", IBM Technical Disclosure Bulletin, vol. 15 (Sep. 1972) pp. 1342-1342a.

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