MOS transistor and its fabricating method

Details MOS transistor and its fabricating method MOS transistor and its fabricating method

1994-09-19

1996-05-21

Thomas, Tom

Fishing, trapping, and vermin destroying

437 41, 437162, H01L 218234

Patent

active

055189440

ABSTRACT:
An object of the subject invention is to offer a MOS semiconductor device capable of suppressing hot carrier degradation, improving driving capabilities and also enabling miniaturization to the submicron region and smaller; and methods for its fabrication. By forming the gate electrode 5 through the medium of gate oxide film 4 on one main surface of the first conductivity type semiconductor substrate 1 between the second conductivity type low concentration diffusion layers 3, the effective channel length is made roughly equal to the gate length, and miniaturization to the submicron region and smaller is accomplished. Also, by forming the second conductivity type diffusion layer 7A on the sides of the gate electrode 5 through the medium of the thin insulating film 6 to be above the low concentration diffusion layer 3 and further contacting the low concentration diffusion layer 3, the high electrical field within the low concentration diffusion layer 3 is sufficiently ameliorated, generation of hot carriers is suppressed, and resistance to degradation is improved. Moreover, by controlling the high resistance second conductivity typetype diffusion layer 7 A at the sides of the gate electrode 5, the source resistance is decreased and driving capabilities are improved. At the same time the contact region of the source-drain electrode is miniaturized.

REFERENCES:
patent: 4788160 (1988-11-01), Havemann et al.
patent: 4837179 (1989-06-01), Foster et al.
patent: 4971922 (1990-02-01), Watabe et al.
patent: 5047361 (1991-09-01), Matloubian et al.
patent: 5089435 (1992-02-01), Akiyama
IH-Chin Chen, "Simple Gate-to-Drian Overlapped MOSFET's Using Poly Spacers for High Immunity to Channel Hot-Electron Degradation," IEEE Electron Device Letters, vol. 11, No. 2, pp. 78-81, Feb.
C. K. Lau et al., "A Super Self-Aligned Source/Drain MOSFET", IEEE, pp. 358-361, 1987.

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