MOS transconductor with broad trimming range

Details MOS transconductor with broad trimming range MOS transconductor with broad trimming range

2000-06-19

2001-08-07

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S563000, C330S253000

Reexamination Certificate

active

06271688

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated electronic circuits, and, more particularly, to a time-continuous analog filter with a programmable cut off frequency.
BACKGROUND OF THE INVENTION
The time constants of integrated systems have been traditionally implemented using transconductors and capacitors (T=C/gm). Cut off programmability is achieved by controlling the transconductance gain gm.
FIG. 1
shows a typical CMOS differential transconductor for which the following equations apply:
ID=
1/2*
u*Cox*W/L*Vod{circumflex over ( )}
2  (1)
where:
Vod=VGS−VTH
gm=dID/dVGS=u*Cox*W/L*Vod
  (2)
where:
ID is the drain current
u is the nobility
Cox is the specific capacitance of
the oxide
W is the channel width
L is the channel length
Vod is the so-called “overdrive” voltage of a MOS transistor
For a given transistor's dimensioning (W/L), the maximum value of the transconductance gain gm is limited by the fact that the overdrive voltage Vod of the differential stage cannot exceed a certain value. Otherwise, the bias current generator of the stage could be turned off. In contrast, the minimum value of the current gain gm is limited by the fact that if the overdrive voltage Vod decreases the same amplitude of the input signal, the distortion that is introduced on the output current delivered by the transconductor stage increases.
The current output by the transconductor is directly proportional to the input voltage Vin only if such current is relatively small if compared to the overdrive voltage Vod. The distortion caused by the transconductor at relatively low values of the overdrive voltage Vod may be reduced by introducing, for this purpose, a number of degeneration resistors, as shown in FIG.
2
.
By defining gm
1
as the transconductance of the single input MOS transistor, the stage transconductance may be expressed as:
gm=gm
1
/(1+
R*gm
1
)  (3)
In the known structure of
FIG. 2
, part of the input signal drops due to the degeneration resistance. Therefore, for the same amplitude of the input signal, the voltage vgs between the gate and the source has a reduced range and a reduced distortion, according to the expression:
vgs
=
vi
*
1
/
gm
⁡
(
R
+
1
/
gm
)
=
vi
/
(
1
+
R
*
gm
)
(
4
)
For the same absorbed power and overdrive, a greater linearity is obtained at the expense of a lower transconductance gain.
A disadvantage of this known structure is that the transconductance attenuation caused by the source degeneration resistance, introduced to improve the linearity at low overdrive levels, increases as the overdrive voltage increases. The result is a reduction of the trimming range of the circuit.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the present invention to overcome the above described limitations and drawbacks of the known differential transconductor circuits.
This and other objects, features and advantages in accordance with the present invention are provided by a degeneration resistance that decreases upon increasing the overdrive voltage. At high overdrive voltage values, there are less distortion problems, and thereby, a lower degree of degeneration is acceptable.
A resistive degeneration line includes one or more transistors in series that are sized to function in a so-called triode region of their characteristic, i.e., the nonsaturated region or ohmic region. The gate of the one or more transistors used to form the resistive line of source degeneration of the differential pair of input transistors may be, according to a first embodiment, coupled to the common voltage mode of the differential stage so that the transistor(s) may function with the same gate/source voltage (vgs) of the differential pair of input transistors.
As long as the drain-source voltage of the degeneration transistors remains lower than the overdrive voltage Vod, they function in the triode region by operating like resistances with a value defined by 1/gds. The drain-source conductance is defined by gds. The degeneration ratio is maintained constant irrespectively of the technological parameters, i.e., the spread of the fabrication process.
According to an alternative and preferred embodiment, which further extends the trimming range of the transconductance stage, the gates of the one or more transistors used to form the resistive line of source degeneration of the differential pair of input transistors are biased by a dedicated circuit. By injecting across a resistance R of the bias circuit to the gate of the one or more transistors used to form the resistive line of source degeneration, a current proportional to the bias current of the differential pair provides a degeneration resistance proportional to 1/(Vod+k*Vod{circumflex over ( )}2), where k=(R*u*Cox/2)*(W
1
/L
1
).


REFERENCES:
patent: 4568885 (1986-02-01), McKenzie et al.
patent: 4573020 (1986-02-01), Whatley
patent: 5384501 (1995-01-01), Koyama et al.
patent: 5642077 (1997-06-01), Nagaraj
patent: 5642078 (1997-06-01), Navabi et al.
patent: 93830284.1 (1993-06-01), None
Visocchi et al., “Fully Balanced Tunable GaAs MESFET OTA-C Integrator Suitable for High Precision Filtering Applications”, Mar. 12, 1992, pp. 537-539.

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