1989-12-29
1991-04-16
Jackson, Jr., Jerome
357 231, 357 2311, 357 49, H01L 2978, H01L 4902, H01L 2713
Patent
active
050087231
ABSTRACT:
Reduction of parasitic coupling capacitances which are otherwise formed between conventional NMOS transistor N type drain regions and the transistor's substrate and well regions is described by using a semiconductor-on-insulator (SOI) substrate and forming the NMOS transistor on a semiconductor (Si) substrate having a buried insulator forming a deep, lightly doped N type subsurface region beneath the conventional surface drain region (but not the source region) which contacts the buried insulator.
REFERENCES:
IEDM, 1987, "Novel Selective in Processing", Mieno et al, pp. 16-19, Dec. 198, Wash., D.C.
Jackson, Jr. Jerome
Kopin Corporation
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