MOS switch that reduces clock feedthrough in a switched...

Details MOS switch that reduces clock feedthrough in a switched... MOS switch that reduces clock feedthrough in a switched...

1999-03-16

2001-01-16

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Utilizing a three or more electrode solid-state device

C327S427000

Reexamination Certificate

active

06175268

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to MOS switches and, more particularly, to a MOS switch that reduces clock feedthrough in a switched capacitor circuit.
2. Description of the Related Art
A MOS transistor is a device that controls a channel current, which flows from the drain to the source of the transistor, in response to a voltage applied to the gate of the transistor. As a result of this ability to control the channel current, MOS transistors are commonly used as voltage-controlled switches where the transistor provides a very-low resistance current path when turned on, and a very-high resistance current path when turned off.
FIGS.
1
A-
1
B show cross-sectional and schematic diagrams, respectively, that illustrate a conventional NMOS transistor
10
. As shown in FIGS.
1
A-
1
B, transistor
10
includes n+ spaced-apart source and drain regions
14
and
16
which are formed in a p-type substrate
12
, and a channel region
18
which is defined between source and drain regions
14
and
16
. In addition, transistor
10
also includes a dielectric layer
20
which is formed over channel region
18
, and a gate
22
which is formed over dielectric layer
20
.
In operation, when voltages are applied to source and drain regions
14
and
16
so that the drain-to-source voltage V
DS
is greater than zero, and a voltage is applied to gate
22
so that the gate-to-source voltage V
GS
is greater than the threshold voltage V
T
, transistor
10
turns on, thereby allowing a channel current I
C
to flow from drain region
16
to source region
14
.
On the other hand, when the drain-to-source voltage V
DS
is greater than zero,. and a voltage is applied to gate
22
so that the gate-to-source voltage V
GS
is equal to or less than the threshold voltage V
T
, transistor
10
turns off, thereby preventing channel current I
C
from flowing from drain
16
to source
14
(except for a leakage current).
One of the most common applications for MOS switches, which are used in a wide variety of applications, is in a switched capacitor circuit. FIGS.
2
A-
2
B show cross-sectional and schematic diagrams, respectively, that illustrate a conventional switched capacitor circuit
50
.
As shown in FIGS.
2
A-
2
B, circuit
50
includes transistor
10
of
FIG. 1 and a
capacitor
52
which is connected between source region
14
and ground. In addition, drain region
16
is connected to receive an input signal V
IN
, while gate
22
is connected to receive a clock signal CLK.
In operation, when the drain-to-source voltage V
DS
is greater than zero, and the gate-to-source voltage V
GS
is greater than the voltage on the source region
14
by the threshold voltage V
T
, transistor
10
turns on. When transistor
10
turns on, a channel current I
C
flows from drain region
16
through source region
14
and charges up capacitor
52
to the voltage of the input signal V
IN
(assuming that the time that the clock signal CLK is high is much greater than the time constant defined by the turn-on resistance of transistor
10
and the capacitance of capacitor
52
).
One drawback to the use of transistor
10
in switched capacitor circuit
50
, however, is that the voltage applied to gate
22
via the clock signal CLK is capacitively coupled to source region
14
via a parasitic gate overlap capacitor C
1
which is formed from gate
22
, dielectric layer
20
, and source region
14
, and via a parasitic lateral fringing field capacitor C
2
formed from gate
22
, an insulation layer formed over source region
14
, and source region
14
.
This capacitive coupling, known as clock feedthrough, causes a small negative charge to accumulate at the surface of source region
14
below gate
22
(the lower plates of the parasitic capacitors C
1
and C
2
), and a corresponding small positive charge to accumulate on the top plate of capacitor
52
when the clock voltage on gate
22
begins to rise, but is insufficient to turn on transistor
10
because the voltage on gate
22
is now greater than the voltage on source region
14
.
Once the clock signal CLK turns transistor
10
on, capacitor
52
, as noted above, charges up to the voltage of the input signal V
IN
. Since capacitor
52
charges up to the input voltage V
IN
, the small positive charge that accumulated on the top plate of capacitor
52
during the preturn-on period presents no problems.
The problem, however, comes after transistor
10
turns off. As the clock voltage on gate
22
continues to fall after transistor
10
has turned off, the capacitive coupling causes a small positive charge to accumulate at the surface of source region
14
below gate
22
(the lower plates of the parasitic capacitors C
1
and C
2
), and a corresponding small negative charge to accumulate on the top plate of capacitor
52
because the voltage on gate
22
is now lower than the voltage on source region
14
.
The small negative charge on the top plate of capacitor
52
functions as a negative offset voltage which, in turn, reduces the magnitude of the voltage held by capacitor
52
. As a result, the voltage held by capacitor
52
at the end of the switched cycle erroneously represents the voltage of the input signal V
IN
by the small negative offset voltage.
One technique for reducing the negative offset voltage is to utilize a switched capacitor circuit with complementary MOS transistors.
FIG. 3
shows a schematic diagram that illustrates a conventional switched capacitor circuit
70
that utilizes complementary MOS transistors.
As shown in
FIG. 3
, circuit
70
includes transistor
10
and capacitor
52
of
FIGS. 2A and 2B
, and a PMOS transistor
72
. As shown, PMOS transistor
72
has a source
74
which is connected to drain
16
of transistor
10
, a drain
76
which is connected to source
14
of transistor
10
, and a gate
78
connected to receive an inverted clock signal /CLK.
In operation, when the clock signal CLK is high and the inverted clock signal /CLK is low, both transistors
10
and
72
are on. After transistors
10
and
72
turn off, the capacitive coupling of NMOS transistor
10
causes a small negative charge to accumulate on the top plate of capacitor
52
, while PMOS transistor
72
causes of small positive charge to accumulate on the top plate of capacitor
52
.
As a result, the negative charge that is injected onto the top plate of capacitor
52
by transistor
10
is theoretically cancelled out by the positive charge that is injected onto the top plate of capacitor
52
by transistor
72
.
In actual practice, however, circuit
70
fails to completely remove the negative charge from capacitor
52
because the feedthrough parasitic capacitances of NMOS transistor
10
are typically not the same as the feedthrough parasitic capacitances of PMOS transistor
72
.
In addition, the turn-on delays of NMOS transistor
10
and PMOS transistor
72
are not the same. As a result, the channel conductances of transistors
10
and
72
will typically not track each other during turn on and turn off. Thus, there is a need for a MOS switch that reduces clock feedthrough in a switched capacitor circuit.
SUMMARY OF THE INVENTION
Conventional MOS-based switched capacitor circuits suffer from the accumulation of a small positive charge on the source of the MOS transistor which occurs after the transistor has been turned off due to the parasitic capacitance that exists between the gate and the source of the transistor.
This small positive charge, known as clock feedthrough, also causes a small negative charge to accumulate on the capacitor which, in turn, prevents another device from accurately reading the voltage stored on the capacitor. In the present invention, clock feedthrough is reduced by utilizing a split-gate transistor, and by continuously biasing one of the gates.
A switched capacitor circuit in accordance with the present invention, which is formed in a semiconductor substrate, includes a transistor that has spaced-apart source and drain regions formed in the substrate, and a channel region which

Affiliated with

Also associated with

Rating

MOS switch that reduces clock feedthrough in a switched... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with MOS switch that reduces clock feedthrough in a switched..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS switch that reduces clock feedthrough in a switched... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2497132