MOS static RAM with improved soft error resistance; high-level s

Details MOS static RAM with improved soft error resistance; high-level s MOS static RAM with improved soft error resistance; high-level s

1996-11-22

1998-03-31

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 365190, 326 93, G11C 800

Patent

active

057346224

ABSTRACT:
An object of the present invention is to provide a MOS static RAM in which the power consumption can be reduced when it is required to reduce the power consumption during standby, and sufficient soft error resistance can be secured when it is required to provide sufficient soft error resistance for the cell. A MOS static RAM of the present invention comprises a power supply circuit for generating a plurality of voltages of different voltage values and a selection circuit for selecting one voltage from among the plurality of voltages output from the power supply circuit and supplying the selected voltage as a cell data retention voltage to a flip-flop that forms a cell.

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