MOS Static RAM layout with polysilicon resistors over FET gates

Details MOS Static RAM layout with polysilicon resistors over FET gates MOS Static RAM layout with polysilicon resistors over FET gates

1980-09-16

1984-06-05

Larkins, William D.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 239, 357 51, 357 59, 365154, H01L 2704, H01L 2978, G11C 1140

Patent

active

044531753

ABSTRACT:
A semiconductor device having a semiconductor substrate, wherein first and second insulating gate FET transistor connected, respectively, in series with first and second polycrystalline silicon layers acting as loads of first and second inverters are formed. The first polycrystalline silicon layer is provided above a gate electrode of the second insulation gate FET transistor, and the second polycrystalline silicon layer is provided above a gate electrode of the first insulation gate FET transistor.

REFERENCES:
patent: 4110776 (1978-08-01), Rao et al.
patent: 4125854 (1978-11-01), McKenny et al.
patent: 4240097 (1980-12-01), Raymond, Jr.
patent: 4322824 (1982-03-01), Allan
patent: 4326213 (1982-04-01), Shirai et al.

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