MOS static memory circuit

Details MOS static memory circuit MOS static memory circuit

1985-11-21

1988-07-26

Hecker, Stuart N.

Static information storage and retrieval

Powering

Conservation of power

365190, G11C 1300, G11C 700

Patent

active

047605626

ABSTRACT:
Voltage converters are arranged in units of columns in a memory device. Each voltage converter is connected to a column decoder. The column decoder receives a column address signal and supplies a column selection signal to the voltage converter. The voltage converters apply a ground level voltage to the source junctions of the drive transistor pairs of the memory cells of the selected columns, and a voltage higher than the ground level voltage to the source junctions of the drive transistor pairs of the memory cells of the nonselected columns so as to decrease power consumption in the nonselected columns as compared with that in the selected columns.

REFERENCES:
patent: 4120047 (1978-10-01), Varadi
patent: 4409679 (1983-10-01), Kurafuji et al.
patent: 4455628 (1984-06-01), Ozaki et al.
patent: 4542486 (1985-09-01), Anami et al.
Minato et al., "A Hi-CMOSII 8K.times.8b Static RAM," IEEE International Solid-State Circuits Conference, Feb. 12, 1982.

Affiliated with

Also associated with

Rating

MOS static memory circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with MOS static memory circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS static memory circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-262318