MOS stage with high output resistance particularly for integrate

Details MOS stage with high output resistance particularly for integrate MOS stage with high output resistance particularly for integrate

1989-02-15

1990-08-28

Miller, Stanley D.

Amplifiers

With semiconductor amplifying device

Including field effect transistor

307500, 307501, H03F 345

Patent

active

049528858

ABSTRACT:
A first N-channel transistor (M1) and a second N-channel transistor (M2) are cascode connected and the source electrode of the first transistor is connected to the ground; a third P-channel transistor (M3) and a fourth P-channel transistor (M4) are also cascode connected, and the source of the fourth transistor is connected to a supply voltage; the drains of the second and third transistors (M2, M3) are mutually connected to act as output terminal. According to the invention, the absolute values of the threshold voltages of the second and third transistors are lower than the threshold voltages of the first and fourth transistors, and the gates of the first and second transistors are furthermore mutually connected to act as input terminal for a voltage signal, while the gates of said third and fourth transistors are mutually connected to act as input terminal for a bias voltage.

REFERENCES:
patent: 3739194 (1973-06-01), Freeman et al.
patent: 4191898 (1980-03-01), Ulmer
patent: 4568844 (1986-02-01), O'Connor
patent: 4687954 (1987-08-01), Yasuda et al.
patent: 4806877 (1989-02-01), Kobayashi
patent: 4835423 (1984-05-01), de Ferron et al.
IEEE Journal of Solid-State Circuits, vol. SC-17, No. 6, Dec., 1982, Gray and Meyer: MOS OP Design--An Overview, pp. 977-978.
Analysis and Design of Analog Integrated Circuits, Second Edition, c. 1977, 1984; Gray and Meyer, pp. 711-714.
CMOS Analog Circuit Design, 1987, Allen and Holberg, pp. 223, 282-283, 296 and 421-426.

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