MOS Sense amplifier

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307578, 307362, 365205, 365208, H03K 524, G11C 706

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active

044121431

ABSTRACT:
A comparator circuit suitably configured and synchronously operated to distinguish between the levels of two input signals and to provide the relative standing of the levels in binary format. In one form, a symmetrically organized circuit having the fundamental structure of a bistable multivibrator is initially operated in a differential mode and subsequently transitioned to a latch mode. Appropriate constant current source biasing shifts the differential mode operation to optimize amplifier element gain characteristics for the levels of input signals received. The amplified difference between the two input signals is stored within various capacitive elements of the circuit output stages. During the differential mode, the bistable multivibrator cross-coupling elements are disabled. At the termination of the differential mode, the amplified difference between the two input signals provides the initial conditions for the regenerative dynamics associated with the onset of cross-coupling and the transition to the latched state. Preferably, the input signals and the bias circuit are disabled in synchronism with the cross-coupling operation, to provide a stable output from the multivibrator circuit in conventional binary format.

REFERENCES:
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patent: 3982140 (1976-09-01), Lockwood
patent: 3983413 (1976-09-01), Gunsagar et al.
patent: 3992637 (1976-11-01), Cassidy et al.
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patent: 4195357 (1980-03-01), Kuo et al.
patent: 4253163 (1981-02-01), Komoriya et al.
Bishop et al., "High-Speed, High-Sensitivity FET Sense Latch", IBM Tech. Discl. Bull.; vol. 18, No. 4, pp. 1021-1022; 9/75.

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