MOS semiconductor process with double-layer gate electrode struc

Details MOS semiconductor process with double-layer gate electrode struc MOS semiconductor process with double-layer gate electrode struc

1988-09-06

1990-02-13

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 49, 437195, 437193, H01L 21316

Patent

active

049006908

ABSTRACT:
A MOS semiconductor device with a double-layer gate electrode structure includes a silicon substrate and a field oxide layer which is selectively formed on one major surface of the substrate in such a manner as to surround an active region. A first silicon oxide layer is deposited in a region of a gate electrode of the semiconductor device. A polycrystalline silicon layer is provided on the first silicon layer and in a portion which extends from the region of the gate electrode to above the field oxide layer. Source and drain diffusion regions are defined in a part of the active region of the major surface of the substrate. An impurity-doped second silicon oxide layer is deposited on the entire surface of a laminate which is constituted by the substrate to the source and drain diffusion regions except for the surface of that portion of the polycrystalline silicon layer which overlies the field oxide layer. A conductive layer is provided on that portion of the second silicon oxide layer which is associated with the region of the gate electrode and extending to above and being connected to that portion of the polycrystalline silicon layer which overlies the field oxide layer. Further, an impurity-doped third silicon oxide layer is deposited on the entire surface of a laminate constituted by the substrate to the conductive layer. A wiring is connected to the source and drain diffusion regions and gate electrode by contact holes which are formed in the third silicon oxide layer.

REFERENCES:
patent: 4367580 (1983-01-01), Guterman
patent: 4373249 (1983-02-01), Kosa et al.
patent: 4533935 (1985-08-01), Mochizuki
patent: 4816425 (1989-03-01), McPherson
Hori, T., et al., "Improvement of Dielectric Strength . . . ", VLSI Symposium 1987, pp. 63-64.

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