MOS Semiconductor process utilizing a two-layer oxide forming te

Metal treatment – Compositions – Heat treating

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

29571, 148174, 148187, 357 23, 357 54, 427 93, 427 95, H01L 21324, H01L 21265, H01L 2131

Patent

active

041405480

ABSTRACT:
Process for the manufacture of MOS devices by providing wafer of P-semiconductor grade silicon in a deposition reactor. The wafer is heated to a temperature of approximately 950.degree. C. while subjecting the wafer to dry oxygen gas to produce between a very thin layer (50-250A) of silica (SiO.sub.2) on a surface of the wafer. While elevating the temperature of the wafer to approximately 1000.degree. C., the chamber is purged with nitrogen and then hydrogen gas. After an introduction of carbon dioxide gas into the chamber, silane (SiH.sub.4) or dichlorosilane gas is bled into the chamber. The silane reacts with the CO.sub.2 to deposit SiO.sub.2 on the previously formed thermal SiO.sub.2. The two layers of SiO.sub.2 may then be annealed to provide a highly coherent, defect-free gate oxide for MOS integrated circuits.

REFERENCES:
patent: 3158505 (1964-11-01), Sandor
patent: 3184329 (1965-05-01), Burns
patent: 3243314 (1966-03-01), Lehman et al.
patent: 3532539 (1970-10-01), Tokuyama et al.
patent: 3547786 (1970-12-01), Rigo
patent: 3580745 (1971-05-01), Kooi et al.
patent: 3615873 (1971-10-01), Sluss et al.
patent: 3627589 (1971-12-01), Sprague
patent: 3925107 (1975-12-01), Goula et al.
Goula, R. A., "Composite Dielectric Layer" I.B.M. Tech. Discl. Bull., vol. 14, No. 9, Feb. 1972, p. 2609.
Bratter et al., "High-Temperature Pyrolytic Deposition Process".
Ibid., vol. 15, No. 2, Jul. 1972, p. 685.
Burkhardt et al., "Post-Oxidation Annealing . . . Levels" Ibid., vol. 18, No. 3, Aug. 1975, p. 753.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

MOS Semiconductor process utilizing a two-layer oxide forming te does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with MOS Semiconductor process utilizing a two-layer oxide forming te, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MOS Semiconductor process utilizing a two-layer oxide forming te will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-256893

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.