MOS semiconductor integrated circuit device

Details MOS semiconductor integrated circuit device MOS semiconductor integrated circuit device

2007-03-06

2007-03-06

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230080

Reexamination Certificate

active

11213877

ABSTRACT:
A first P-channel transistor is connected between a gate of an N-channel transistor constituting a last-stage buffer circuit and an output of a prebuffer circuit. A second P-channel transistor is connected between the power supply node and a gate of a P-channel transistor constituting a last-stage buffer circuit. A first N-channel transistor is connected between an N-channel transistor constituting the prebuffer circuit and the ground potential supply node. A second N-channel transistor is connected between the power supply node and a P-channel transistor constituting the main buffer circuit.

REFERENCES:
patent: 5602796 (1997-02-01), Sugio
patent: 5886942 (1999-03-01), Akita
patent: 5912857 (1999-06-01), Kim et al.
patent: 6665229 (2003-12-01), Lee et al.
Masanao Yamaoka, et al., “A 300MHz 25 μA/Mb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone Application Processor”, 2004 IEEE International Solid-State Circuits Conference / Session 27 / SRAM / 27.2, Digest of Technical Papers, Salon 10-15, Feb. 18, 2004, pp. 494-495.
Koji Nii, et al., “A 90 nm Low Power 32K-Byte Embedded SRAM with Gate Leakage Suppression Circuit for Mobile Applications”, 2003 Symposium on VLSI Circuits Digest of Technical Papers, 2003, pp. 247-250.

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