Semiconductor device manufacturing: process – Making passive device
Reexamination Certificate
1999-02-09
2001-02-20
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
C438S386000, C438S391000
Reexamination Certificate
active
06190987
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, particularly a capacitive element, having a metal-oxide-semiconductor (MOS) structure formed on a semiconductor substrate.
2. Description of the Prior Art
Capacitive elements formed on the surface of a semiconductor substrate are used in various semiconductor devices. Examples are a capacitive element for holding electric charge in a dynamic random-access memory (DRAM), a couple capacitive element connected crosswise to a bit line pair in a multi-level storage DRAM, and a capacitive element in an analog-to-digital (A-D) comparator. The capacitance of a couple capacitive element has an influence on the accuracy of a multi-level storage sensing operation. The capacitance of a capacitive element used in an A-D comparator has an influence on the accuracy of A-D conversion. Accordingly, these capacitive elements formed are required to have a highly accurate capacitance.
Capacitive elements generally have a metal-insulator-metal (MIM) structure and a metal-insulator-semiconductor (MIS) structure. A metal-oxide-semiconductor (MOS) structure as one MIS structure, in which the insulator is an oxide, can be fabricated by the same formation steps as a MOS field-effect transistor as a principal element constituting a semiconductor device. Therefore, a MOS structure has been most often used as a MOS capacitor.
A MOS structure often used as a MOS capacitor comprises a diffusion layer formed on the surface of a semiconductor substrate and having a conductivity type different from that of the semiconductor substrate, an oxide film (generally a silicon oxide film) formed on the surface of the diffusion layer, and a conductor layer formed on the silicon oxide film. The diffusion layer functions as one electrode, and the conductor layer functions as the other electrode. This MOS structure operates as a MOS capacitor when a voltage is applied between these two electrodes.
FIGS. 1A and 1B
are a plan view and a sectional view showing the planar structure and the sectional structure, respectively, of a conventional MOS capacitor commonly used. In
FIGS. 1A and 1B
, reference numeral
101
denotes a P-type silicon substrate;
102
, an N channel doped layer formed by lightly doping an N-type impurity such as phosphorus into the surface of the P-type silicon substrate
101
;
103
, a gate oxide film made of a silicon oxide film formed on the major surface of the P-type silicon substrate including the channel doped layer
102
;
104
, a first gate electrode formed on the gate oxide film
103
in the region of the channel doped layer
102
and made from polycrystalline silicon doped with an N-type impurity; and
105
, a first N
+
diffusion layer formed by heavily doping an N-type impurity in the major surface of the P-type silicon substrate
101
around the gate electrode
104
. This first N
+
diffusion layer
105
is formed by implanting ions of an impurity such as phosphorus at a high concentration by using the first gate electrode
104
as a mask and performing annealing to diffuse the phosphorus as an impurity. Consequently, the layer is heavily doped to a region deeper than the channel doped layer
102
. Also, the first N
+
diffusion layer
105
diffuses in the lateral direction due to annealing and enters slightly inside the outer peripheral portion of the first gate electrode
104
. In this manner, a MOS capacitor is fabricated which has the first gate electrode
104
formed on the gate oxide film
103
as one electrode and the first N
+
diffusion layer
105
formed below the gate oxide film
103
and connected to the channel doped layer
102
as the other electrode.
This MOS capacitor shows an operating characteristic as shown in
FIG. 2
when a voltage is applied between the two electrodes. That is, when a gate voltage VG applied to the first gate electrode is higher than a reference voltage applied to the first N
+
diffusion layer, i.e., when a positive voltage is applied, a storage state in which a negative electric charge in the channel doped layer
102
is accumulated in the surface portion is set, and a capacitance C1 takes a fixed value. When VG is shifted from a positive voltage to a negative voltage, the capacitance C1 is fixed until a predetermined negative voltage VGd. The value of VGd depends upon the work function of the first gate electrode, the impurity concentration in the channel doped layer, and the film thickness of the gate oxide film. When VG is further shifted to a negative voltage, a negative electric charge in the channel doped layer in the vicinity of the gate oxide film
103
is gradually pushed in the direction of depth, and a depletion layer having no free electric charge extends in the direction of depth on the surface of the channel doped layer
102
. The formation of this depletion layer depends upon the impurity concentration in the channel doped layer
102
, and the magnitude of the negative voltage applied to the gate oxide film and the gate electrode. When VG is further shifted to a predetermined negative voltage VGa or lower at which the width of the depletion layer reaches a maximum value, an inversion layer having a positive electric charge is formed on the surface of the channel doped layer
102
, and the capacitance C1 takes a fixed value. As described above, when the N-type impurity concentration in the channel doped layer
102
is low, the full capacitance C1 of the MOS capacitor is obtained by connecting, in series, a capacitance Cox of the gate oxide film and a capacitance Cs1, which depends upon the gate voltage VG, of the depletion layer and the inversion layer, as shown in
FIG. 3
, and is represented by equation (1) below.
1/C1=(1/Cox)+(1/Cs1) (1)
As the impurity concentration in the channel doped layer
102
increases, the depletion layer width decreases, and so the second term on the right side of equation (1) decreases. On the other hand, almost no depletion layer is formed in a region where the first gate electrode
104
and the first N
+
diffusion layer
105
with a sufficiently high impurity concentration overlap each other with the gate oxide film
103
between them. Accordingly, the second term on the right side of equation (1) becomes a negligibly small value. The capacitance in this overlap region is represented only by the first term on the right side of equation (1), i.e., by the capacitance Cox of the gate oxide film.
As described above, in the MOS capacitor shown in
FIGS. 1A and 1B
in which the impurity concentration in the channel doped layer
102
is low and the channel doped layer
102
immediately below the first gate electrode
104
occupies a large area, the capacitance C1 of the MOS capacitor at negative voltages lower than VGd largely changes with applied voltage. This is a serious problem in a couple capacitance or a capacitive element used in an A-D comparator.
As one prior art for alleviating the above problem that the capacitance C1 of a MOS transistor lowers at negative voltages, a semiconductor device is disclosed in Japanese Unexamined Patent Publication No. 1-146351.
FIGS. 4A and 4B
are a plan view and a sectional view for explaining the planar structure and the sectional structure, respectively, of the semiconductor device disclosed in Japanese Unexamined Patent Publication No. 1-146351. Note that a description of the same parts as in
FIGS. 1A and 1B
will be omitted. In
FIGS. 4A and 4B
, reference numerals
101
to
103
denote the same components as in the prior art shown in
FIGS. 1A and 1B
;
106
, a rectangular second gate electrode serving as a first conductive layer;
107
, rectangular apertures; and
108
, a second N
+
diffusion layer as an impurity region serving as a second conductive layer. In the second gate electrode
106
, five apertures
107
are formed in each of the longitudinal and lateral directions. The second N
+
diffusion layer
108
is formed in a region corresponding to the outer peripheral portion of the seco
Kasai Naoki
Koga Hiroki
Chaudhuri Olik
Coleman William David
NEC Corporation
Young & Thompson
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