MOS semiconductor device

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307297, G11C 1140

Patent

active

046987894

ABSTRACT:
An MOS semiconductor device comprises a MOS operation circuit including a plurality of MOS transistors each with a reduced channel length and an operation voltage setting circuit for supplying an operation voltage lower than the power source voltage between the first and second operation voltage receiving terminals. The back gates of the MOS transistors in the MOS operation circuit are connected to a power source terminal or ground. The operation voltage setting circuit is inserted between the MOS operation circuit and either the power source terminal or ground and develops a voltage drop in accordance with the operating current flowing through the MOS operation circuit.

REFERENCES:
patent: 4260909 (1981-04-01), Dumbri et al.
patent: 4585955 (1986-04-01), Uchida
Itoh et al., "An Experimental 1MB DRAM with On-Chip Voltage Limiter," IEEE International Solid-State Circuits Conference, pp. 282, 283, Feb. 24, 1984.

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