MOS resistance controlling device and MOS attenuator

Details MOS resistance controlling device and MOS attenuator MOS resistance controlling device and MOS attenuator

2007-11-07

2010-02-16

Cox, Cassandra (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S108000

Reexamination Certificate

active

07663420

ABSTRACT:
A MOS resistance controlling device includes: a plurality of MOS transistors having a first MOS transistor to N-th (the integer N is larger than 1) MOS transistor being serially connected, the source of the first MOS transistor being set to a first reference potential, the drain the N-th MOS transistor being set to a second reference potential, and the drain of an I-th MOS transistor being connected to the source of an I+1-th MOS transistor, where I is an integer from 1 to N−1; a current source which is electrically disposed at connection node between the drain of the N-th MOS transistors and the second reference potential; and an operational amplifier having a first input terminal being supplied with a third reference potential, a second input terminal connected with the connection node and an output terminal being connected with gates of the MOS transistors.

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Dogan et al, A DC-10GHz Linear-in-dB Attenuator in 0.13um CMOS Technology, IEEE 2004 Custom Integrated Circuits Conference, pp. 609-612.
Dogan, et al; IEEE 2004 Custom Integrated Circuit Conference; “A DC-10GHZ Linear-in-DB Attenuatror in . . . ”.
Japanese Office Action mailed Oct. 28, 2008 corresponding to U.S. Appl. No. 11/936,214, filed on Nov. 7, 2007.

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