MOS read-only memory device

Details MOS read-only memory device MOS read-only memory device

1986-07-29

1988-08-02

Popek, Joseph A.

Static information storage and retrieval

Addressing

365203, G11C 700

Patent

active

047617691

ABSTRACT:
An MOS type read-only memory device having a reduced power consumption has a clock signal generator circuit for generating a pair of positive and negative clock signals by detecting a change of an address signal in the ROM having MOS transistors used as a load and connected to bit lines, a tri-state circuit including an input, a control signal input, and an ouput; the tri-state circuit has its output impedance made higher due to a clock signal supplied to the control signal input. The device also has a switching circuit for keeping the MOS transistors used as a load in their active state based on a clock signal. The inputs and outputs of the tri-state circuit are each connected to the bit lines and gates of the MOS transistors used as a load. The switching circuit is connected to the gate side of the MOS transistors used as a load.

REFERENCES:
patent: 4417328 (1983-11-01), Ochii
patent: 4592028 (1986-05-01), Konishi
"Introduction to VLSI System" C. Mead & L. Conway, pp. 79-82.

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