MOS random access memory device with an internal voltage-down co

Static information storage and retrieval – Powering

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365149, 365203, 365204, 36523006, G11C 1300

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active

053982070

ABSTRACT:
A MOS dynamic random access memory device has a memory cell array section formed on a semiconductor substrate, including memory cells each having a data storage capacitor and a transfer-gate transistor. Parallel bit lines are associated with the memory cell array section. Parallel word lines extend transverse to the bit lines, including a word line connected to the transfer-gate transistor. A booster circuit is arranged to provide a potentially raised voltage which is higher than a power supply voltage. A sense amplifier circuit is connected with a corresponding bit line pair of the word lines. A word-line driver circuit has an input connected to the booster circuit and an output connected to the word line. A bit-line restoring circuit is connected to the sense amplifier circuit. The restoring circuit includes a voltage-down converting metal oxide semiconductor field effect transistor having an insulated gate connected to the booster circuit, a drain coupled to the power supply voltage, and a source at which a potentially decreased voltage appears to be lower than the power supply voltage. The voltage-down converting transistor is same in channel conductivity type as the transfer-gate transistor.

REFERENCES:
patent: 5103113 (1992-04-01), Inui et al.
patent: 5249155 (1993-09-01), Arimoto et al.
IEEE Journal Of Solid-State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1170-1175, Syuso Fujii, et al., "A 45-ns 16-Mbit DRAM With Triple-Well Structure."

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