MOS pull-up or pull-down logic circuit having equalized discharg

Details MOS pull-up or pull-down logic circuit having equalized discharg MOS pull-up or pull-down logic circuit having equalized discharg

1983-07-29

1987-12-29

Miller, Stanley D.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307443, 307448, 307357, 307579, 357 2314, 357 45, 357 71, H03K 19017, H01L 2704, H01L 2978

Patent

active

047163089

ABSTRACT:
A MOS logic circuit comprises two P channel MOSFETs connected in parallel between a positive power source V.sub.DD and a logic signal output terminal and two series circuits connected in parallel between a ground voltage source V.sub.SS and the terminal, each series circuit being comprised of serially connected two N channel MOSFETs. The gate electrodes of the MOSFETs located in the corresponding positions in the respective series circuits are connected to first and second logic signal input terminals, respectively. Similarly, the gate electrodes of the other MOSFETs located in the corresponding positions in the respective series circuits are connected to the second and first logic signal input terminals, respectively.

REFERENCES:
patent: 3900742 (1975-08-01), Hampel et al.
patent: 3945000 (1976-03-01), Suzuki et al.
patent: 4074151 (1978-02-01), Buckley et al.
patent: 4367420 (1983-01-01), Foss et al.
patent: 4394586 (1983-07-01), Morozumi
patent: 4401903 (1983-08-01), Iizuka
patent: 4489246 (1984-12-01), Nishiuchi
patent: 4507574 (1985-03-01), Seki et al.
Mead & Conway, Introduction to VLSI Design, Addison-Wesley Pub. Co., Reading, Mass, Oct. 1980, plate, p. 152.
U.S. patent application Ser. No. 116,556 filed on Jan. 29, 1980.

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