MOS power stage for generating non-overlapping two-phase clock s

Details MOS power stage for generating non-overlapping two-phase clock s MOS power stage for generating non-overlapping two-phase clock s

1976-10-29

1977-08-30

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307220R, 307265, 307269, H03K 118, H03K 515, H03K 5156, H03K 504

Patent

active

040456854

ABSTRACT:
This relates to an MOS power stage of a two-phase clock signal generator arranged on the same integrated circuit chip as the circuit to be driven. The generator consists of one MOSFET inverter, the output of which is multiplexed by the two clock signals. In this manner, power loss in the MOSFET is reduced.

REFERENCES:
patent: 3479603 (1969-11-01), Overstreet, Jr.
patent: 3536936 (1970-10-01), Rubinstein et al.
patent: 3641366 (1972-02-01), Fujimoto
patent: 3777184 (1973-12-01), Smith
patent: 3805167 (1974-04-01), Nash et al.
patent: 3870962 (1975-03-01), D'Errico
patent: 3986046 (1976-10-01), Wunner

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