MOS output circuit

Details MOS output circuit MOS output circuit

1991-01-23

1992-07-21

Mottola, Steven

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

365190, G11C 700

Patent

active

051325748

ABSTRACT:
An output circuit for a memory device has four MOS transistors. A first MOS transistor and a second MOS transistor comprise an output stage of the output circuit, and a control circuit controls the voltages of the gates of the first and the second MOS transistors. A third MOS transistor has its source connected to the gate of the second MOS transistor, and a fourth MOS transistor has its source connected to the gate of the first MOS transistor. When the data which are supplied to the control circuit are changed, the third or the fourth MOS transistor assists the level shift of the gate of the second and the first MOS transistor at the beginning of the level shift. By continuing the level shift, the third or the fourth MOS transistor is turned off. As a result, the source-gate voltage of the third or the fourth MOS transistor becomes lower than its threshold voltage, so that the switching noise or ground noise is reduced.

REFERENCES:
patent: 4144590 (1979-03-01), Kitagawa
patent: 4397000 (1983-08-01), Nagani
patent: 4604731 (1986-08-01), Konishi
IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988; "A 7.5-ns 32 K.times.8 CMOS SRAM", by Hiroaki Okuyama et al., pp. 1054-1059.

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