Communications: electrical – Digital comparator systems
Patent
1976-04-12
1977-08-30
Fears, Terrell W.
Communications: electrical
Digital comparator systems
340173CA, 340173FF, 307238, G11C 1140
Patent
active
040457834
ABSTRACT:
A dynamic MOS one transistor cell memory having a plurality of divided bit lines and a corresponding plurality of flip-flop sense amplifiers. Each bit line being divided into two electrically balanced parts which run adjacent and parallel to each other, and extend from the input/output nodes of their corresponding flip-flop sense amplifier to a balanced data access bus. The balanced data access bus being connected, in turn, to balanced data access, or read/write, circuitry. By virtue of the connection of balanced bit, and bus lines, and balanced data access circuitry, to each flip-flop sense amplifier, the probability of reading errors due to circuit imbalances at the input/output nodes of the flip-flops is greatly lessened. The direct connection, from the read/write circuitry to both parts of each bit line, arising from this arrangement obviates the need to enable a flip-flop sense amplifier in order to perform a writing operation, and permits a read-modify-write operation with flip-flop sense amplifiers designed with dynamic loads.
REFERENCES:
patent: 3949381 (1976-04-01), Dennard
patent: 3967252 (1976-06-01), Donnelly
patent: 4003035 (1977-01-01), Hoffmann
DeLuca Alfred A.
Fears Terrell W.
Standard Microsystems Corporation
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