Patent
1989-02-21
1991-01-15
James, Andrew J.
357 54, 357 90, 357 91, 357 233, H01L 2978
Patent
active
049857177
ABSTRACT:
A semiconductor memory device having a CMOS memory cell with a floating gate and increasing concentration of dopant in the source, drain and channel regions. Typically the concentration profile is generally exponential across the channel width. The device has relatively high diffusion current densities accelerated toward the surface and directed toward the channel/drain interface. Gate oxidation thickness is reduced over the channel near the drain to create a tunnel "window" in the area of greatest electric field magnitude. The device provides for significantly reduced write times as compared to conventional devices.
REFERENCES:
patent: 4878101 (1989-11-01), Hsieh et al.
Aronowitz Sheldon
Forsythe Donald D.
Gadepally Bhaskar V. S.
Walker George P.
Dang Xuan Hung
James Andrew J.
National Semiconductor
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