MOS master-slave flip-flop with reduced number of pass gates

Details MOS master-slave flip-flop with reduced number of pass gates MOS master-slave flip-flop with reduced number of pass gates

1996-08-13

1998-11-03

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327203, 327199, H03K 19173, H03K 33562

Patent

active

058314636

ABSTRACT:
A master-slave flip-flop has master and slave latches cascaded between an input and an output. Each latch has two inverters directly connected to one another head to tail. The latches are coupled via a buffer and a clock controlled pass gate. This architecture reduces the number of pass gates and clock lines, improves hold time and enhances I.sub.DDQ -testability with respect to known flip-flops.

REFERENCES:
patent: 4495628 (1985-01-01), Zasio
patent: 4656368 (1987-04-01), McComb et al.
patent: 5107137 (1992-04-01), Kinugasa
patent: 5189315 (1993-02-01), Akata
patent: 5612632 (1997-03-01), Mahant-Shetti et al.

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