MOS manufacturing process having reduced gate insulator defects

Details MOS manufacturing process having reduced gate insulator defects MOS manufacturing process having reduced gate insulator defects

1992-10-23

1995-04-18

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 56, 437913, H01L 21265

Patent

active

054078393

ABSTRACT:
A method for reducing implant-induced damage and residual photo-resist-induced damage to a gate insulator layer first forms a gate insulator layer on portions of a semiconductor substrate. A first gate electrode layer is formed over the gate insulator layer, this first gate electrode layer being thinner than the desired final gate electrode thickness. A threshold adjustment implant is performed through the first, thin, gate electrode layer and underlying gate insulator layer. A second gate electrode layer is formed over the first gate electrode layer such that the thickness of the first and second gate electrode layers are substantially equal to the desired final gate electrode thickness. The first and second gate electrode layers are then patterned concurrently by conventional photolithography processes to form the gate electrodes. These steps prevent the attachment of resist particles to the gate insulator layer and prevent the ion implant-induced damage to the gate insulator by using the first gate electrode layer as a buffer.

REFERENCES:
patent: 4966866 (1990-10-01), Mikata et al.
patent: 5028552 (1991-07-01), Ushiku
patent: 5032530 (1991-07-01), Lowery et al
patent: 5210042 (1993-05-01), Oshikawa

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