MOS/LSI Time delay circuit

Details MOS/LSI Time delay circuit MOS/LSI Time delay circuit

1982-07-02

1985-03-05

Miller, Stanley D.

Electrical transmission or interconnection systems

With nonswitching means responsive to external nonelectrical...

Temperature responsive

307443, 307481, 307246, 307582, 307269, 307594, 307601, H03K 17284, H03K 17693, H03K 19094

Patent

active

045033455

ABSTRACT:
A time delay circuit having a voltage reference node adapted to receive a reference voltage from a reference voltage source, the time delay circuit comprising: a resistor, a capacitance means having a first and second node, the first node being connected to a reference potential, such as ground, the resistor being connected between the input signal node and the capacitance means second node, a first field effect transistor having a gate and a conduction channel having a first and second terminal, the first field effect transistor gate being connected to the voltage reference node, the first field effect transistor conduction channel second terminal being connected to the capacitance means second node, the first field effect transistor conduction channel first terminal being connected to the output signal node,

REFERENCES:
patent: 4196362 (1980-04-01), Maehashi
patent: 4300065 (1981-11-01), Remedi et al.
patent: 4388538 (1983-06-01), Ikeda
patent: 4409501 (1983-10-01), Eickerman et al.
patent: 4430587 (1984-02-01), Tennyson

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